// Copyright (C) 2022 Beken Corporation
// 
// Licensed under the Apache License, Version 2.0 (the "License");           
// you may not use this file except in compliance with the License.            
// You may obtain a copy of the License at                                     
//                                                                             
//     http://www.apache.org/licenses/LICENSE-2.0                              
//                                                                             
// Unless required by applicable law or agreed to in writing, software         
// distributed under the License is distributed on an "AS IS" BASIS,         
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.    
// See the License for the specific language governing permissions and         
// limitations under the License.                                              

/***********************************************************************************************************************************
* This file is generated from BK7256_ADDR Mapping_20211224_format_change_highlight_20220113_update.xlsm automatically                                
* Modify it manually is not recommended                                       
* CHIP ID:BK7256,GENARATE TIME:2022-03-17 20:29:39                                                 
************************************************************************************************************************************/

#pragma once                 
                            
#ifdef __cplusplus          
extern "C" {              
#endif                      

#define SYS_LL_REG_BASE      (SOC_SYSTEM_REG_BASE)

/* REG_0x00 */
#define SYS_DEVICE_ID_ADDR  (SYS_LL_REG_BASE  + 0x0*4) //REG ADDR :0x44010000
#define SYS_DEVICE_ID_DEVICEID_POS (0) 
#define SYS_DEVICE_ID_DEVICEID_MASK (0xFFFFFFFF) 

/* REG_0x01 */
#define SYS_VERSION_ID_ADDR  (SYS_LL_REG_BASE  + 0x1*4) //REG ADDR :0x44010004
#define SYS_VERSION_ID_VERSIONID_POS (0) 
#define SYS_VERSION_ID_VERSIONID_MASK (0xFFFFFFFF) 

/* REG_0x02 */
#define SYS_CPU_CURRENT_RUN_STATUS_ADDR  (SYS_LL_REG_BASE  + 0x2*4) //REG ADDR :0x44010008
#define SYS_CPU_CURRENT_RUN_STATUS_CORE0_HALTED_POS (0) 
#define SYS_CPU_CURRENT_RUN_STATUS_CORE0_HALTED_MASK (0x1) 

#define SYS_CPU_CURRENT_RUN_STATUS_CORE1_HALTED_POS (1) 
#define SYS_CPU_CURRENT_RUN_STATUS_CORE1_HALTED_MASK (0x1) 

#define SYS_CPU_CURRENT_RUN_STATUS_RESERVED2_POS (2) 
#define SYS_CPU_CURRENT_RUN_STATUS_RESERVED2_MASK (0x3) 

#define SYS_CPU_CURRENT_RUN_STATUS_CPU0_SW_RESET_POS (4) 
#define SYS_CPU_CURRENT_RUN_STATUS_CPU0_SW_RESET_MASK (0x1) 

#define SYS_CPU_CURRENT_RUN_STATUS_CPU1_SW_RESET_POS (5) 
#define SYS_CPU_CURRENT_RUN_STATUS_CPU1_SW_RESET_MASK (0x1) 

#define SYS_CPU_CURRENT_RUN_STATUS_RESERVED1_POS (6) 
#define SYS_CPU_CURRENT_RUN_STATUS_RESERVED1_MASK (0x3) 

#define SYS_CPU_CURRENT_RUN_STATUS_CPU0_PWR_DW_STATE_POS (8) 
#define SYS_CPU_CURRENT_RUN_STATUS_CPU0_PWR_DW_STATE_MASK (0x1) 

#define SYS_CPU_CURRENT_RUN_STATUS_CPU1_PWR_DW_STATE_POS (9) 
#define SYS_CPU_CURRENT_RUN_STATUS_CPU1_PWR_DW_STATE_MASK (0x1) 

#define SYS_CPU_CURRENT_RUN_STATUS_RESERVED0_POS (10) 
#define SYS_CPU_CURRENT_RUN_STATUS_RESERVED0_MASK (0x3FFFFF) 

/* REG_0x03 */
#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_ADDR  (SYS_LL_REG_BASE  + 0x3*4) //REG ADDR :0x4401000c
#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_BOOT_MODE_POS (0) 
#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_BOOT_MODE_MASK (0x1) 

#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_RESERVED2_POS (1) 
#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_RESERVED2_MASK (0x7) 

#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_RF_SWITCH_EN_POS (4) 
#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_RF_SWITCH_EN_MASK (0x1) 

#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_RF_FOR_WIFIORBT_POS (5) 
#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_RF_FOR_WIFIORBT_MASK (0x1) 

#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_RESERVED1_POS (6) 
#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_RESERVED1_MASK (0x3) 

#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_JTAG_CORE_SEL_POS (8) 
#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_JTAG_CORE_SEL_MASK (0x1) 

#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_FLASH_SEL_POS (9) 
#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_FLASH_SEL_MASK (0x1) 

#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_RESERVED0_POS (10) 
#define SYS_CPU_STORAGE_CONNECT_OP_SELECT_RESERVED0_MASK (0x3FFFFF) 

/* REG_0x04 */
#define SYS_CPU0_INT_HALT_CLK_OP_ADDR  (SYS_LL_REG_BASE  + 0x4*4) //REG ADDR :0x44010010
#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_SW_RST_POS (0) 
#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_SW_RST_MASK (0x1) 

#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_PWR_DW_POS (1) 
#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_PWR_DW_MASK (0x1) 

#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_INT_MASK_POS (2) 
#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_INT_MASK_MASK (0x1) 

#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_HALT_POS (3) 
#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_HALT_MASK (0x1) 

#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_CLK_DIV_POS (4) 
#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_CLK_DIV_MASK (0xF) 

#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_OFFSET_POS (8) 
#define SYS_CPU0_INT_HALT_CLK_OP_CPU0_OFFSET_MASK (0xFFFFFF) 

/* REG_0x05 */
#define SYS_CPU1_INT_HALT_CLK_OP_ADDR  (SYS_LL_REG_BASE  + 0x5*4) //REG ADDR :0x44010014
#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_SW_RST_POS (0) 
#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_SW_RST_MASK (0x1) 

#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_PWR_DW_POS (1) 
#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_PWR_DW_MASK (0x1) 

#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_INT_MASK_POS (2) 
#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_INT_MASK_MASK (0x1) 

#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_HALT_POS (3) 
#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_HALT_MASK (0x1) 

#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_CLK_DIV_POS (4) 
#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_CLK_DIV_MASK (0xF) 

#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_OFFSET_POS (8) 
#define SYS_CPU1_INT_HALT_CLK_OP_CPU1_OFFSET_MASK (0xFFFFFF) 

/* REG_0x06 */
#define SYS_RESERVED_REG0X6_ADDR  (SYS_LL_REG_BASE  + 0x6*4) //REG ADDR :0x44010018
#define SYS_RESERVED_REG0X6_RESERVED_POS (0) 
#define SYS_RESERVED_REG0X6_RESERVED_MASK (0xFFFFFFFF) 

/* REG_0x08 */
#define SYS_CPU_CLK_DIV_MODE1_ADDR  (SYS_LL_REG_BASE  + 0x8*4) //REG ADDR :0x44010020
#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_CORE_POS (0) 
#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_CORE_MASK (0xF) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_CORE_POS (4) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_CORE_MASK (0x3) 

#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_BUS_POS (6) 
#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_BUS_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_RESERVED0_POS (7) 
#define SYS_CPU_CLK_DIV_MODE1_RESERVED0_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_UART0_POS (8) 
#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_UART0_MASK (0x3) 

#define SYS_CPU_CLK_DIV_MODE1_CLKSEL_UART0_POS (10) 
#define SYS_CPU_CLK_DIV_MODE1_CLKSEL_UART0_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_UART1_POS (11) 
#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_UART1_MASK (0x3) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_UART1_POS (13) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_UART1_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_UART2_POS (14) 
#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_UART2_MASK (0x3) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_UART2_POS (16) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_UART2_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_SADC_POS (17) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_SADC_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_PWM0_POS (18) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_PWM0_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_PWM1_POS (19) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_PWM1_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_TIMER0_POS (20) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_TIMER0_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_TIMER1_POS (21) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_TIMER1_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_TIMER2_POS (22) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_TIMER2_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_CAN_POS (23) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_CAN_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_I2S_POS (24) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_I2S_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_AUD_POS (25) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_AUD_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_JPEG_POS (26) 
#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_JPEG_MASK (0xF) 

#define SYS_CPU_CLK_DIV_MODE1_CKSEL_JPEG_POS (30) 
#define SYS_CPU_CLK_DIV_MODE1_CKSEL_JPEG_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_DISP_L_POS (31) 
#define SYS_CPU_CLK_DIV_MODE1_CLKDIV_DISP_L_MASK (0x1) 

/* REG_0x09 */
#define SYS_CPU_CLK_DIV_MODE2_ADDR  (SYS_LL_REG_BASE  + 0x9*4) //REG ADDR :0x44010024
#define SYS_CPU_CLK_DIV_MODE2_CLKDIV_DISP_H_POS (0) 
#define SYS_CPU_CLK_DIV_MODE2_CLKDIV_DISP_H_MASK (0x7) 

#define SYS_CPU_CLK_DIV_MODE2_CKSEL_DISP_POS (3) 
#define SYS_CPU_CLK_DIV_MODE2_CKSEL_DISP_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE2_CKDIV_PSRAM_POS (4) 
#define SYS_CPU_CLK_DIV_MODE2_CKDIV_PSRAM_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE2_CKSEL_PSRAM_POS (5) 
#define SYS_CPU_CLK_DIV_MODE2_CKSEL_PSRAM_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE2_CKDIV_QSPI0_POS (6) 
#define SYS_CPU_CLK_DIV_MODE2_CKDIV_QSPI0_MASK (0xF) 

#define SYS_CPU_CLK_DIV_MODE2_CKSEL_QSPI0_POS (10) 
#define SYS_CPU_CLK_DIV_MODE2_CKSEL_QSPI0_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE2_RESERVED_POS (11) 
#define SYS_CPU_CLK_DIV_MODE2_RESERVED_MASK (0x7) 

#define SYS_CPU_CLK_DIV_MODE2_CKDIV_SDIO_POS (14) 
#define SYS_CPU_CLK_DIV_MODE2_CKDIV_SDIO_MASK (0x7) 

#define SYS_CPU_CLK_DIV_MODE2_CKSEL_SDIO_POS (17) 
#define SYS_CPU_CLK_DIV_MODE2_CKSEL_SDIO_MASK (0x1) 

#define SYS_CPU_CLK_DIV_MODE2_CKDIV_AUXS_POS (18) 
#define SYS_CPU_CLK_DIV_MODE2_CKDIV_AUXS_MASK (0xF) 

#define SYS_CPU_CLK_DIV_MODE2_CKSEL_AUXS_POS (22) 
#define SYS_CPU_CLK_DIV_MODE2_CKSEL_AUXS_MASK (0x3) 

#define SYS_CPU_CLK_DIV_MODE2_CKSEL_FLASH_POS (24) 
#define SYS_CPU_CLK_DIV_MODE2_CKSEL_FLASH_MASK (0x3) 

#define SYS_CPU_CLK_DIV_MODE2_CKDIV_FLASH_POS (26) 
#define SYS_CPU_CLK_DIV_MODE2_CKDIV_FLASH_MASK (0x3) 

#define SYS_CPU_CLK_DIV_MODE2_CKDIV_I2S0_POS (28) 
#define SYS_CPU_CLK_DIV_MODE2_CKDIV_I2S0_MASK (0x7) 

#define SYS_CPU_CLK_DIV_MODE2_RESERVED0_POS (31) 
#define SYS_CPU_CLK_DIV_MODE2_RESERVED0_MASK (0x1) 

/* REG_0x0A */
#define SYS_CPU_26M_WDT_CLK_DIV_ADDR  (SYS_LL_REG_BASE  + 0xA*4) //REG ADDR :0x44010028
#define SYS_CPU_26M_WDT_CLK_DIV_CKDIV_26M_POS (0) 
#define SYS_CPU_26M_WDT_CLK_DIV_CKDIV_26M_MASK (0x3) 

#define SYS_CPU_26M_WDT_CLK_DIV_CKDIV_WDT_POS (2) 
#define SYS_CPU_26M_WDT_CLK_DIV_CKDIV_WDT_MASK (0x3) 

#define SYS_CPU_26M_WDT_CLK_DIV_CLKSEL_SPI0_POS (4) 
#define SYS_CPU_26M_WDT_CLK_DIV_CLKSEL_SPI0_MASK (0x1) 

#define SYS_CPU_26M_WDT_CLK_DIV_CLKSEL_SPI1_POS (5) 
#define SYS_CPU_26M_WDT_CLK_DIV_CLKSEL_SPI1_MASK (0x1) 

#define SYS_CPU_26M_WDT_CLK_DIV_RESERVED0_POS (6) 
#define SYS_CPU_26M_WDT_CLK_DIV_RESERVED0_MASK (0x3FFFFFF) 

/* REG_0x0B */
#define SYS_CPU_ANASPI_FREQ_ADDR  (SYS_LL_REG_BASE  + 0xB*4) //REG ADDR :0x4401002c
#define SYS_CPU_ANASPI_FREQ_ANASPI_FREQ_POS (0) 
#define SYS_CPU_ANASPI_FREQ_ANASPI_FREQ_MASK (0x3F) 

#define SYS_CPU_ANASPI_FREQ_RESERVED1_POS (6) 
#define SYS_CPU_ANASPI_FREQ_RESERVED1_MASK (0x3) 

#define SYS_CPU_ANASPI_FREQ_ANAREG_STATE_POS (8) 
#define SYS_CPU_ANASPI_FREQ_ANAREG_STATE_MASK (0xFFFFF) 

#define SYS_CPU_ANASPI_FREQ_RESERVED0_POS (28) 
#define SYS_CPU_ANASPI_FREQ_RESERVED0_MASK (0xF) 

/* REG_0x0C */
#define SYS_CPU_DEVICE_CLK_ENABLE_ADDR  (SYS_LL_REG_BASE  + 0xC*4) //REG ADDR :0x44010030
#define SYS_CPU_DEVICE_CLK_ENABLE_I2C0_CKEN_POS (0) 
#define SYS_CPU_DEVICE_CLK_ENABLE_I2C0_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_SPI0_CKEN_POS (1) 
#define SYS_CPU_DEVICE_CLK_ENABLE_SPI0_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_UART0_CKEN_POS (2) 
#define SYS_CPU_DEVICE_CLK_ENABLE_UART0_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_PWM0_CKEN_POS (3) 
#define SYS_CPU_DEVICE_CLK_ENABLE_PWM0_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_TIM0_CKEN_POS (4) 
#define SYS_CPU_DEVICE_CLK_ENABLE_TIM0_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_SADC_CKEN_POS (5) 
#define SYS_CPU_DEVICE_CLK_ENABLE_SADC_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_IRDA_CKEN_POS (6) 
#define SYS_CPU_DEVICE_CLK_ENABLE_IRDA_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_EFUSE_CKEN_POS (7) 
#define SYS_CPU_DEVICE_CLK_ENABLE_EFUSE_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_I2C1_CKEN_POS (8) 
#define SYS_CPU_DEVICE_CLK_ENABLE_I2C1_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_SPI1_CKEN_POS (9) 
#define SYS_CPU_DEVICE_CLK_ENABLE_SPI1_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_UART1_CKEN_POS (10) 
#define SYS_CPU_DEVICE_CLK_ENABLE_UART1_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_UART2_CKEN_POS (11) 
#define SYS_CPU_DEVICE_CLK_ENABLE_UART2_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_PWM1_CKEN_POS (12) 
#define SYS_CPU_DEVICE_CLK_ENABLE_PWM1_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_TIM1_CKEN_POS (13) 
#define SYS_CPU_DEVICE_CLK_ENABLE_TIM1_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_TIM2_CKEN_POS (14) 
#define SYS_CPU_DEVICE_CLK_ENABLE_TIM2_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_OTP_CKEN_POS (15) 
#define SYS_CPU_DEVICE_CLK_ENABLE_OTP_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_I2S_CKEN_POS (16) 
#define SYS_CPU_DEVICE_CLK_ENABLE_I2S_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_USB_CKEN_POS (17) 
#define SYS_CPU_DEVICE_CLK_ENABLE_USB_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_CAN_CKEN_POS (18) 
#define SYS_CPU_DEVICE_CLK_ENABLE_CAN_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_PSRAM_CKEN_POS (19) 
#define SYS_CPU_DEVICE_CLK_ENABLE_PSRAM_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_QSPI0_CKEN_POS (20) 
#define SYS_CPU_DEVICE_CLK_ENABLE_QSPI0_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_QSPI1_CKEN_POS (21) 
#define SYS_CPU_DEVICE_CLK_ENABLE_QSPI1_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_SDIO_CKEN_POS (22) 
#define SYS_CPU_DEVICE_CLK_ENABLE_SDIO_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_AUXS_CKEN_POS (23) 
#define SYS_CPU_DEVICE_CLK_ENABLE_AUXS_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_BTDM_CKEN_POS (24) 
#define SYS_CPU_DEVICE_CLK_ENABLE_BTDM_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_XVR_CKEN_POS (25) 
#define SYS_CPU_DEVICE_CLK_ENABLE_XVR_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_MAC_CKEN_POS (26) 
#define SYS_CPU_DEVICE_CLK_ENABLE_MAC_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_PHY_CKEN_POS (27) 
#define SYS_CPU_DEVICE_CLK_ENABLE_PHY_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_JPEG_CKEN_POS (28) 
#define SYS_CPU_DEVICE_CLK_ENABLE_JPEG_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_DISP_CKEN_POS (29) 
#define SYS_CPU_DEVICE_CLK_ENABLE_DISP_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_AUD_CKEN_POS (30) 
#define SYS_CPU_DEVICE_CLK_ENABLE_AUD_CKEN_MASK (0x1) 

#define SYS_CPU_DEVICE_CLK_ENABLE_WDT_CKEN_POS (31) 
#define SYS_CPU_DEVICE_CLK_ENABLE_WDT_CKEN_MASK (0x1) 

/* REG_0x0D */
#define SYS_RESERVER_REG0XD_ADDR  (SYS_LL_REG_BASE  + 0xD*4) //REG ADDR :0x44010034
#define SYS_RESERVER_REG0XD_RESERVED_POS (0) 
#define SYS_RESERVER_REG0XD_RESERVED_MASK (0xFFFFFFFF) 

/* REG_0x0E */
#define SYS_CPU_MODE_DISCKG1_ADDR  (SYS_LL_REG_BASE  + 0xE*4) //REG ADDR :0x44010038
#define SYS_CPU_MODE_DISCKG1_AON_DISCKG_POS (0) 
#define SYS_CPU_MODE_DISCKG1_AON_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_SYS_DISCKG_POS (1) 
#define SYS_CPU_MODE_DISCKG1_SYS_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_DMA_DISCKG_POS (2) 
#define SYS_CPU_MODE_DISCKG1_DMA_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_FLASH_DISCKG_POS (3) 
#define SYS_CPU_MODE_DISCKG1_FLASH_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_WDT_DISCKG_POS (4) 
#define SYS_CPU_MODE_DISCKG1_WDT_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_TIM_DISCKG_POS (5) 
#define SYS_CPU_MODE_DISCKG1_TIM_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_URT_DISCKG_POS (6) 
#define SYS_CPU_MODE_DISCKG1_URT_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_PWM_DISCKG_POS (7) 
#define SYS_CPU_MODE_DISCKG1_PWM_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_I2C_DISCKG_POS (8) 
#define SYS_CPU_MODE_DISCKG1_I2C_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_SPI_DISCKG_POS (9) 
#define SYS_CPU_MODE_DISCKG1_SPI_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_SADC_DISCKG_POS (10) 
#define SYS_CPU_MODE_DISCKG1_SADC_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_EFS_DISCKG_POS (11) 
#define SYS_CPU_MODE_DISCKG1_EFS_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_IRDA_DISCKG_POS (12) 
#define SYS_CPU_MODE_DISCKG1_IRDA_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_TRNG_DISCKG_POS (13) 
#define SYS_CPU_MODE_DISCKG1_TRNG_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_SDIO_DISCKG_POS (14) 
#define SYS_CPU_MODE_DISCKG1_SDIO_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_LA_DISCKG_POS (15) 
#define SYS_CPU_MODE_DISCKG1_LA_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_TIM1_DISCKG_POS (16) 
#define SYS_CPU_MODE_DISCKG1_TIM1_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_URT1_DISCKG_POS (17) 
#define SYS_CPU_MODE_DISCKG1_URT1_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_URT2_DISCKG_POS (18) 
#define SYS_CPU_MODE_DISCKG1_URT2_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_PWM1_DISCKG_POS (19) 
#define SYS_CPU_MODE_DISCKG1_PWM1_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_I2C1_DISCKG_POS (20) 
#define SYS_CPU_MODE_DISCKG1_I2C1_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_SPI1_DISCKG_POS (21) 
#define SYS_CPU_MODE_DISCKG1_SPI1_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_USB_DISCKG_POS (22) 
#define SYS_CPU_MODE_DISCKG1_USB_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_CAN_DISCKG_POS (23) 
#define SYS_CPU_MODE_DISCKG1_CAN_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_QSPI0_DISCKG_POS (24) 
#define SYS_CPU_MODE_DISCKG1_QSPI0_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_PSRAM_DISCKG_POS (25) 
#define SYS_CPU_MODE_DISCKG1_PSRAM_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_FFT_DISCKG_POS (26) 
#define SYS_CPU_MODE_DISCKG1_FFT_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_SBC_DISCKG_POS (27) 
#define SYS_CPU_MODE_DISCKG1_SBC_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_AUD_DISCKG_POS (28) 
#define SYS_CPU_MODE_DISCKG1_AUD_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_I2S_DISCKG_POS (29) 
#define SYS_CPU_MODE_DISCKG1_I2S_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_JPEG_DISCKG_POS (30) 
#define SYS_CPU_MODE_DISCKG1_JPEG_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG1_JPEG_DEC_DISCKG_POS (31) 
#define SYS_CPU_MODE_DISCKG1_JPEG_DEC_DISCKG_MASK (0x1) 

/* REG_0x0F */
#define SYS_CPU_MODE_DISCKG2_ADDR  (SYS_LL_REG_BASE  + 0xF*4) //REG ADDR :0x4401003c
#define SYS_CPU_MODE_DISCKG2_DISP_DISCKG_POS (0) 
#define SYS_CPU_MODE_DISCKG2_DISP_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG2_DMA2D_DISCKG_POS (1) 
#define SYS_CPU_MODE_DISCKG2_DMA2D_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG2_RESERVED_POS (2) 
#define SYS_CPU_MODE_DISCKG2_RESERVED_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG2_BTDM_DISCKG_POS (3) 
#define SYS_CPU_MODE_DISCKG2_BTDM_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG2_XVER_DISCKG_POS (4) 
#define SYS_CPU_MODE_DISCKG2_XVER_DISCKG_MASK (0x1) 

#define SYS_CPU_MODE_DISCKG2_BTDM_BPS_CKG_POS (5) 
#define SYS_CPU_MODE_DISCKG2_BTDM_BPS_CKG_MASK (0xF) 

#define SYS_CPU_MODE_DISCKG2_RESERVED0_POS (9) 
#define SYS_CPU_MODE_DISCKG2_RESERVED0_MASK (0x7FFFFF) 

/* REG_0x10 */
#define SYS_CPU_POWER_SLEEP_WAKEUP_ADDR  (SYS_LL_REG_BASE  + 0x10*4) //REG ADDR :0x44010040
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_MEM1_POS (0) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_MEM1_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_MEM2_POS (1) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_MEM2_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_MEM3_POS (2) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_MEM3_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_ENCP_POS (3) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_ENCP_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_BAKP_POS (4) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_BAKP_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_AHBP_POS (5) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_AHBP_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_AUDP_POS (6) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_AUDP_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_VIDP_POS (7) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_VIDP_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_BTSP_POS (8) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_BTSP_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_WIFP_MAC_POS (9) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_WIFP_MAC_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_WIFP_PHY_POS (10) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_WIFP_PHY_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_MEM0_POS (11) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_PWD_MEM0_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_RESERVED1_POS (12) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_RESERVED1_MASK (0xF) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_SLEEP_EN_NEED_FLASH_IDLE_POS (16) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_SLEEP_EN_NEED_FLASH_IDLE_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_SLEEP_EN_NEED_CPU1_WFI_POS (17) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_SLEEP_EN_NEED_CPU1_WFI_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_SLEEP_EN_NEED_CPU0_WFI_POS (18) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_SLEEP_EN_NEED_CPU0_WFI_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_SLEEP_EN_GLOBAL_POS (19) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_SLEEP_EN_GLOBAL_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_WIFI_WAKEUP_PLATFORM_EN_POS (20) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_WIFI_WAKEUP_PLATFORM_EN_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_BTS_WAKEUP_PLATFORM_EN_POS (21) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_BTS_WAKEUP_PLATFORM_EN_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_BTS_SLEEP_EXIT_REQ_POS (22) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_BTS_SLEEP_EXIT_REQ_MASK (0x1) 

#define SYS_CPU_POWER_SLEEP_WAKEUP_RESERVED0_POS (23) 
#define SYS_CPU_POWER_SLEEP_WAKEUP_RESERVED0_MASK (0x1FF) 

/* REG_0x11 */
#define SYS_RESERVER_REG0X11_ADDR  (SYS_LL_REG_BASE  + 0x11*4) //REG ADDR :0x44010044
#define SYS_RESERVER_REG0X11_RESERVED_POS (0) 
#define SYS_RESERVER_REG0X11_RESERVED_MASK (0xFFFFFFFF) 

/* REG_0x20 */
#define SYS_CPU0_INT_0_31_EN_ADDR  (SYS_LL_REG_BASE  + 0x20*4) //REG ADDR :0x44010080
#define SYS_CPU0_INT_0_31_EN_CPU0_BMC32_INT_EN_POS (0) 
#define SYS_CPU0_INT_0_31_EN_CPU0_BMC32_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_HOST_0_IRQ_EN_POS (1) 
#define SYS_CPU0_INT_0_31_EN_CPU0_HOST_0_IRQ_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_HOST_0_SEC_IRQ_EN_POS (2) 
#define SYS_CPU0_INT_0_31_EN_CPU0_HOST_0_SEC_IRQ_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_TIMER_INT_EN_POS (3) 
#define SYS_CPU0_INT_0_31_EN_CPU0_TIMER_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_UART_INT_EN_POS (4) 
#define SYS_CPU0_INT_0_31_EN_CPU0_UART_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_PWM_INT_EN_POS (5) 
#define SYS_CPU0_INT_0_31_EN_CPU0_PWM_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_I2C_INT_EN_POS (6) 
#define SYS_CPU0_INT_0_31_EN_CPU0_I2C_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_SPI_INT_EN_POS (7) 
#define SYS_CPU0_INT_0_31_EN_CPU0_SPI_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_SADC_INT_EN_POS (8) 
#define SYS_CPU0_INT_0_31_EN_CPU0_SADC_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_IRDA_INT_EN_POS (9) 
#define SYS_CPU0_INT_0_31_EN_CPU0_IRDA_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_SDIO_INT_EN_POS (10) 
#define SYS_CPU0_INT_0_31_EN_CPU0_SDIO_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_GDMA_INT_EN_POS (11) 
#define SYS_CPU0_INT_0_31_EN_CPU0_GDMA_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_LA_INT_EN_POS (12) 
#define SYS_CPU0_INT_0_31_EN_CPU0_LA_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_TIMER1_INT_EN_POS (13) 
#define SYS_CPU0_INT_0_31_EN_CPU0_TIMER1_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_I2C1_INT_EN_POS (14) 
#define SYS_CPU0_INT_0_31_EN_CPU0_I2C1_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_UART1_INT_EN_POS (15) 
#define SYS_CPU0_INT_0_31_EN_CPU0_UART1_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_UART2_INT_EN_POS (16) 
#define SYS_CPU0_INT_0_31_EN_CPU0_UART2_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_SPI1_INT_EN_POS (17) 
#define SYS_CPU0_INT_0_31_EN_CPU0_SPI1_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_CAN_INT_EN_POS (18) 
#define SYS_CPU0_INT_0_31_EN_CPU0_CAN_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_USB_INT_EN_POS (19) 
#define SYS_CPU0_INT_0_31_EN_CPU0_USB_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_QSPI_INT_EN_POS (20) 
#define SYS_CPU0_INT_0_31_EN_CPU0_QSPI_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_FFT_INT_EN_POS (21) 
#define SYS_CPU0_INT_0_31_EN_CPU0_FFT_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_SBC_INT_EN_POS (22) 
#define SYS_CPU0_INT_0_31_EN_CPU0_SBC_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_AUD_INT_EN_POS (23) 
#define SYS_CPU0_INT_0_31_EN_CPU0_AUD_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_I2S_INT_EN_POS (24) 
#define SYS_CPU0_INT_0_31_EN_CPU0_I2S_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_JPEGENC_INT_EN_POS (25) 
#define SYS_CPU0_INT_0_31_EN_CPU0_JPEGENC_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_JPEGDEC_INT_EN_POS (26) 
#define SYS_CPU0_INT_0_31_EN_CPU0_JPEGDEC_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_LCD_INT_EN_POS (27) 
#define SYS_CPU0_INT_0_31_EN_CPU0_LCD_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_DMA2D_INT_EN_POS (28) 
#define SYS_CPU0_INT_0_31_EN_CPU0_DMA2D_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_WIFI_INT_PHY_MPB_EN_POS (29) 
#define SYS_CPU0_INT_0_31_EN_CPU0_WIFI_INT_PHY_MPB_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_WIFI_INT_PHY_RIU_EN_POS (30) 
#define SYS_CPU0_INT_0_31_EN_CPU0_WIFI_INT_PHY_RIU_EN_MASK (0x1) 

#define SYS_CPU0_INT_0_31_EN_CPU0_WIFI_MAC_INT_TX_RX_TIMER_EN_POS (31) 
#define SYS_CPU0_INT_0_31_EN_CPU0_WIFI_MAC_INT_TX_RX_TIMER_EN_MASK (0x1) 

/* REG_0x21 */
#define SYS_CPU0_INT_32_63_EN_ADDR  (SYS_LL_REG_BASE  + 0x21*4) //REG ADDR :0x44010084
#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_TX_RX_MISC_EN_POS (0) 
#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_TX_RX_MISC_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_RX_TRIGGER_EN_POS (1) 
#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_RX_TRIGGER_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_TX_TRIGGER_EN_POS (2) 
#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_TX_TRIGGER_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_PROT_TRIGGER_EN_POS (3) 
#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_PROT_TRIGGER_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_GEN_EN_POS (4) 
#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_MAC_INT_GEN_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_HSU_IRQ_EN_POS (5) 
#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_HSU_IRQ_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_INT_MAC_WAKEUP_EN_POS (6) 
#define SYS_CPU0_INT_32_63_EN_CPU0_WIFI_INT_MAC_WAKEUP_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_DM_IRQ_EN_POS (7) 
#define SYS_CPU0_INT_32_63_EN_CPU0_DM_IRQ_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_BLE_IRQ_EN_POS (8) 
#define SYS_CPU0_INT_32_63_EN_CPU0_BLE_IRQ_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_BT_IRQ_EN_POS (9) 
#define SYS_CPU0_INT_32_63_EN_CPU0_BT_IRQ_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_RESERVED2_POS (10) 
#define SYS_CPU0_INT_32_63_EN_RESERVED2_MASK (0x3F) 

#define SYS_CPU0_INT_32_63_EN_CPU0_MBOX0_INT_EN_POS (16) 
#define SYS_CPU0_INT_32_63_EN_CPU0_MBOX0_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_MBOX1_INT_EN_POS (17) 
#define SYS_CPU0_INT_32_63_EN_CPU0_MBOX1_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_BMC64_INT_EN_POS (18) 
#define SYS_CPU0_INT_32_63_EN_CPU0_BMC64_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_RESERVED3_POS (19) 
#define SYS_CPU0_INT_32_63_EN_RESERVED3_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_TOUCHED_INT_EN_POS (20) 
#define SYS_CPU0_INT_32_63_EN_CPU0_TOUCHED_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_USBPLUG_INT_EN_POS (21) 
#define SYS_CPU0_INT_32_63_EN_CPU0_USBPLUG_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_RTC_INT_EN_POS (22) 
#define SYS_CPU0_INT_32_63_EN_CPU0_RTC_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_CPU0_GPIO_INT_EN_POS (23) 
#define SYS_CPU0_INT_32_63_EN_CPU0_GPIO_INT_EN_MASK (0x1) 

#define SYS_CPU0_INT_32_63_EN_RESERVED4_POS (24) 
#define SYS_CPU0_INT_32_63_EN_RESERVED4_MASK (0xFF) 

/* REG_0x22 */
#define SYS_CPU1_INT_0_31_EN_ADDR  (SYS_LL_REG_BASE  + 0x22*4) //REG ADDR :0x44010088
#define SYS_CPU1_INT_0_31_EN_CPU1_BMC32_INT_EN_POS (0) 
#define SYS_CPU1_INT_0_31_EN_CPU1_BMC32_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_HOST_0_IRQ_EN_POS (1) 
#define SYS_CPU1_INT_0_31_EN_CPU1_HOST_0_IRQ_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_HOST_0_SEC_IRQ_EN_POS (2) 
#define SYS_CPU1_INT_0_31_EN_CPU1_HOST_0_SEC_IRQ_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_TIMER_INT_EN_POS (3) 
#define SYS_CPU1_INT_0_31_EN_CPU1_TIMER_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_UART_INT_EN_POS (4) 
#define SYS_CPU1_INT_0_31_EN_CPU1_UART_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_PWM_INT_EN_POS (5) 
#define SYS_CPU1_INT_0_31_EN_CPU1_PWM_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_I2C_INT_EN_POS (6) 
#define SYS_CPU1_INT_0_31_EN_CPU1_I2C_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_SPI_INT_EN_POS (7) 
#define SYS_CPU1_INT_0_31_EN_CPU1_SPI_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_SADC_INT_EN_POS (8) 
#define SYS_CPU1_INT_0_31_EN_CPU1_SADC_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_IRDA_INT_EN_POS (9) 
#define SYS_CPU1_INT_0_31_EN_CPU1_IRDA_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_SDIO_INT_EN_POS (10) 
#define SYS_CPU1_INT_0_31_EN_CPU1_SDIO_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_GDMA_INT_EN_POS (11) 
#define SYS_CPU1_INT_0_31_EN_CPU1_GDMA_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_LA_INT_EN_POS (12) 
#define SYS_CPU1_INT_0_31_EN_CPU1_LA_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_TIMER1_INT_EN_POS (13) 
#define SYS_CPU1_INT_0_31_EN_CPU1_TIMER1_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_I2C1_INT_EN_POS (14) 
#define SYS_CPU1_INT_0_31_EN_CPU1_I2C1_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_UART1_INT_EN_POS (15) 
#define SYS_CPU1_INT_0_31_EN_CPU1_UART1_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_UART2_INT_EN_POS (16) 
#define SYS_CPU1_INT_0_31_EN_CPU1_UART2_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_SPI1_INT_EN_POS (17) 
#define SYS_CPU1_INT_0_31_EN_CPU1_SPI1_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_CAN_INT_EN_POS (18) 
#define SYS_CPU1_INT_0_31_EN_CPU1_CAN_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_USB_INT_EN_POS (19) 
#define SYS_CPU1_INT_0_31_EN_CPU1_USB_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_QSPI_INT_EN_POS (20) 
#define SYS_CPU1_INT_0_31_EN_CPU1_QSPI_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_FFT_INT_EN_POS (21) 
#define SYS_CPU1_INT_0_31_EN_CPU1_FFT_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_SBC_INT_EN_POS (22) 
#define SYS_CPU1_INT_0_31_EN_CPU1_SBC_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_AUD_INT_EN_POS (23) 
#define SYS_CPU1_INT_0_31_EN_CPU1_AUD_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_I2S_INT_EN_POS (24) 
#define SYS_CPU1_INT_0_31_EN_CPU1_I2S_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_JPEGENC_INT_EN_POS (25) 
#define SYS_CPU1_INT_0_31_EN_CPU1_JPEGENC_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_JPEGDEC_INT_EN_POS (26) 
#define SYS_CPU1_INT_0_31_EN_CPU1_JPEGDEC_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_LCD_INT_EN_POS (27) 
#define SYS_CPU1_INT_0_31_EN_CPU1_LCD_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_DMA2D_INT_EN_POS (28) 
#define SYS_CPU1_INT_0_31_EN_CPU1_DMA2D_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_WIFI_INT_PHY_MPB_EN_POS (29) 
#define SYS_CPU1_INT_0_31_EN_CPU1_WIFI_INT_PHY_MPB_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_WIFI_INT_PHY_RIU_EN_POS (30) 
#define SYS_CPU1_INT_0_31_EN_CPU1_WIFI_INT_PHY_RIU_EN_MASK (0x1) 

#define SYS_CPU1_INT_0_31_EN_CPU1_WIFI_MAC_INT_TX_RX_TIMER_EN_POS (31) 
#define SYS_CPU1_INT_0_31_EN_CPU1_WIFI_MAC_INT_TX_RX_TIMER_EN_MASK (0x1) 

/* REG_0x23 */
#define SYS_CPU1_INT_32_63_EN_ADDR  (SYS_LL_REG_BASE  + 0x23*4) //REG ADDR :0x4401008c
#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_MAC_INT_TX_RX_MISC_EN_POS (0) 
#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_MAC_INT_TX_RX_MISC_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_MAC_INT_RX_TRIGGER_EN_POS (1) 
#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_MAC_INT_RX_TRIGGER_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_MAC_INT_TX_TRIGGER_EN_POS (2) 
#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_MAC_INT_TX_TRIGGER_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_MAC_INT_PROT_TRIGGER_EN_POS (3) 
#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_MAC_INT_PROT_TRIGGER_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_MAC_INT_GEN_EN_POS (4) 
#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_MAC_INT_GEN_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_HSU_IRQ_EN_POS (5) 
#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_HSU_IRQ_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_INT_MAC_WAKEUP_EN_POS (6) 
#define SYS_CPU1_INT_32_63_EN_CPU1_WIFI_INT_MAC_WAKEUP_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_DM_IRQ_EN_POS (7) 
#define SYS_CPU1_INT_32_63_EN_CPU1_DM_IRQ_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_BLE_IRQ_EN_POS (8) 
#define SYS_CPU1_INT_32_63_EN_CPU1_BLE_IRQ_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_BT_IRQ_EN_POS (9) 
#define SYS_CPU1_INT_32_63_EN_CPU1_BT_IRQ_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_RESERVED2_POS (10) 
#define SYS_CPU1_INT_32_63_EN_RESERVED2_MASK (0x3F) 

#define SYS_CPU1_INT_32_63_EN_CPU1_MBOX0_INT_EN_POS (16) 
#define SYS_CPU1_INT_32_63_EN_CPU1_MBOX0_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_MBOX1_INT_EN_POS (17) 
#define SYS_CPU1_INT_32_63_EN_CPU1_MBOX1_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_BMC64_INT_EN_POS (18) 
#define SYS_CPU1_INT_32_63_EN_CPU1_BMC64_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_RESERVED3_POS (19) 
#define SYS_CPU1_INT_32_63_EN_RESERVED3_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_TOUCHED_INT_EN_POS (20) 
#define SYS_CPU1_INT_32_63_EN_CPU1_TOUCHED_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_USBPLUG_INT_EN_POS (21) 
#define SYS_CPU1_INT_32_63_EN_CPU1_USBPLUG_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_RTC_INT_EN_POS (22) 
#define SYS_CPU1_INT_32_63_EN_CPU1_RTC_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_CPU1_GPIO_INT_EN_POS (23) 
#define SYS_CPU1_INT_32_63_EN_CPU1_GPIO_INT_EN_MASK (0x1) 

#define SYS_CPU1_INT_32_63_EN_RESERVED4_POS (24) 
#define SYS_CPU1_INT_32_63_EN_RESERVED4_MASK (0xFF) 

/* REG_0x28 */
#define SYS_CPU0_INT_0_31_STATUS_ADDR  (SYS_LL_REG_BASE  + 0x28*4) //REG ADDR :0x440100a0
#define SYS_CPU0_INT_0_31_STATUS_CPU0_BMC32_INT_ST_POS (0) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_BMC32_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_HOST_0_IRQ_ST_POS (1) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_HOST_0_IRQ_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_HOST_0_SEC_IRQ_ST_POS (2) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_HOST_0_SEC_IRQ_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_TIMER_INT_ST_POS (3) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_TIMER_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_UART_INT_ST_POS (4) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_UART_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_PWM_INT_ST_POS (5) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_PWM_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_I2C_INT_ST_POS (6) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_I2C_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_SPI_INT_ST_POS (7) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_SPI_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_SADC_INT_ST_POS (8) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_SADC_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_IRDA_INT_ST_POS (9) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_IRDA_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_SDIO_INT_ST_POS (10) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_SDIO_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_GDMA_INT_ST_POS (11) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_GDMA_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_LA_INT_ST_POS (12) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_LA_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_TIMER1_INT_ST_POS (13) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_TIMER1_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_I2C1_INT_ST_POS (14) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_I2C1_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_UART1_INT_ST_POS (15) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_UART1_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_UART2_INT_ST_POS (16) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_UART2_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_SPI1_INT_ST_POS (17) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_SPI1_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_CAN_INT_ST_POS (18) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_CAN_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_USB_INT_ST_POS (19) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_USB_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_QSPI_INT_ST_POS (20) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_QSPI_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_FFT_INT_ST_POS (21) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_FFT_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_SBC_INT_ST_POS (22) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_SBC_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_AUD_INT_ST_POS (23) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_AUD_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_I2S_INT_ST_POS (24) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_I2S_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_JPEGENC_INT_ST_POS (25) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_JPEGENC_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_JPEGDEC_INT_ST_POS (26) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_JPEGDEC_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_LCD_INT_ST_POS (27) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_LCD_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_RESERVED_POS (28) 
#define SYS_CPU0_INT_0_31_STATUS_RESERVED_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_WIFI_INT_PHY_MPB_ST_POS (29) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_WIFI_INT_PHY_MPB_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_WIFI_INT_PHY_RIU_ST_POS (30) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_WIFI_INT_PHY_RIU_ST_MASK (0x1) 

#define SYS_CPU0_INT_0_31_STATUS_CPU0_WIFI_MAC_INT_TX_RX_TIMER_ST_POS (31) 
#define SYS_CPU0_INT_0_31_STATUS_CPU0_WIFI_MAC_INT_TX_RX_TIMER_ST_MASK (0x1) 

/* REG_0x29 */
#define SYS_CPU0_INT_32_63_STATUS_ADDR  (SYS_LL_REG_BASE  + 0x29*4) //REG ADDR :0x440100a4
#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_MAC_INT_TX_RX_MISC_ST_POS (0) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_MAC_INT_TX_RX_MISC_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_MAC_INT_RX_TRIGGER_ST_POS (1) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_MAC_INT_RX_TRIGGER_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_MAC_INT_TX_TRIGGER_ST_POS (2) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_MAC_INT_TX_TRIGGER_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_MAC_INT_PROT_TRIGGER_ST_POS (3) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_MAC_INT_PROT_TRIGGER_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_MAC_INT_GEN_ST_POS (4) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_MAC_INT_GEN_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_HSU_IRQ_ST_POS (5) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_HSU_IRQ_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_INT_MAC_WAKEUP_ST_POS (6) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_WIFI_INT_MAC_WAKEUP_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_DM_IRQ_ST_POS (7) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_DM_IRQ_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_BLE_IRQ_ST_POS (8) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_BLE_IRQ_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_BT_IRQ_ST_POS (9) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_BT_IRQ_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_RESERVED2_POS (10) 
#define SYS_CPU0_INT_32_63_STATUS_RESERVED2_MASK (0x3F) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_MBOX0_INT_ST_POS (16) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_MBOX0_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_MBOX1_INT_ST_POS (17) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_MBOX1_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_BMC64_INT_ST_POS (18) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_BMC64_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_RESERVED3_POS (19) 
#define SYS_CPU0_INT_32_63_STATUS_RESERVED3_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_TOUCHED_INT_ST_POS (20) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_TOUCHED_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_USBPLUG_INT_ST_POS (21) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_USBPLUG_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_RTC_INT_ST_POS (22) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_RTC_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_CPU0_GPIO_INT_ST_POS (23) 
#define SYS_CPU0_INT_32_63_STATUS_CPU0_GPIO_INT_ST_MASK (0x1) 

#define SYS_CPU0_INT_32_63_STATUS_RESERVED4_POS (24) 
#define SYS_CPU0_INT_32_63_STATUS_RESERVED4_MASK (0xFF) 

/* REG_0x2A */
#define SYS_CPU1_INT_0_31_STATUS_ADDR  (SYS_LL_REG_BASE  + 0x2A*4) //REG ADDR :0x440100a8
#define SYS_CPU1_INT_0_31_STATUS_CPU1_BMC32_INT_ST_POS (0) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_BMC32_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_HOST_0_IRQ_ST_POS (1) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_HOST_0_IRQ_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_HOST_0_SEC_IRQ_ST_POS (2) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_HOST_0_SEC_IRQ_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_TIMER_INT_ST_POS (3) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_TIMER_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_UART_INT_ST_POS (4) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_UART_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_PWM_INT_ST_POS (5) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_PWM_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_I2C_INT_ST_POS (6) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_I2C_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_SPI_INT_ST_POS (7) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_SPI_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_SADC_INT_ST_POS (8) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_SADC_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_IRDA_INT_ST_POS (9) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_IRDA_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_SDIO_INT_ST_POS (10) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_SDIO_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_GDMA_INT_ST_POS (11) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_GDMA_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_LA_INT_ST_POS (12) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_LA_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_TIMER1_INT_ST_POS (13) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_TIMER1_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_I2C1_INT_ST_POS (14) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_I2C1_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_UART1_INT_ST_POS (15) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_UART1_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_UART2_INT_ST_POS (16) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_UART2_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_SPI1_INT_ST_POS (17) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_SPI1_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_CAN_INT_ST_POS (18) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_CAN_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_USB_INT_ST_POS (19) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_USB_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_QSPI_INT_ST_POS (20) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_QSPI_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_FFT_INT_ST_POS (21) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_FFT_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_SBC_INT_ST_POS (22) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_SBC_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_AUD_INT_ST_POS (23) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_AUD_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_I2S_INT_ST_POS (24) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_I2S_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_JPEGENC_INT_ST_POS (25) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_JPEGENC_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_JPEGDEC_INT_ST_POS (26) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_JPEGDEC_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_LCD_INT_ST_POS (27) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_LCD_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_RESERVED_POS (28) 
#define SYS_CPU1_INT_0_31_STATUS_RESERVED_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_WIFI_INT_PHY_MPB_ST_POS (29) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_WIFI_INT_PHY_MPB_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_WIFI_INT_PHY_RIU_ST_POS (30) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_WIFI_INT_PHY_RIU_ST_MASK (0x1) 

#define SYS_CPU1_INT_0_31_STATUS_CPU1_WIFI_MAC_INT_TX_RX_TIMER_ST_POS (31) 
#define SYS_CPU1_INT_0_31_STATUS_CPU1_WIFI_MAC_INT_TX_RX_TIMER_ST_MASK (0x1) 

/* REG_0x2B */
#define SYS_CPU1_INT_32_63_STATUS_ADDR  (SYS_LL_REG_BASE  + 0x2B*4) //REG ADDR :0x440100ac
#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_MAC_INT_TX_RX_MISC_ST_POS (0) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_MAC_INT_TX_RX_MISC_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_MAC_INT_RX_TRIGGER_ST_POS (1) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_MAC_INT_RX_TRIGGER_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_MAC_INT_TX_TRIGGER_ST_POS (2) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_MAC_INT_TX_TRIGGER_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_MAC_INT_PROT_TRIGGER_ST_POS (3) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_MAC_INT_PROT_TRIGGER_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_MAC_INT_GEN_ST_POS (4) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_MAC_INT_GEN_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_HSU_IRQ_ST_POS (5) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_HSU_IRQ_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_INT_MAC_WAKEUP_ST_POS (6) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_WIFI_INT_MAC_WAKEUP_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_DM_IRQ_ST_POS (7) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_DM_IRQ_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_BLE_IRQ_ST_POS (8) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_BLE_IRQ_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_BT_IRQ_ST_POS (9) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_BT_IRQ_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_RESERVED2_POS (10) 
#define SYS_CPU1_INT_32_63_STATUS_RESERVED2_MASK (0x3F) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_MBOX0_INT_ST_POS (16) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_MBOX0_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_MBOX1_INT_ST_POS (17) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_MBOX1_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_BMC64_INT_ST_POS (18) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_BMC64_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_RESERVED3_POS (19) 
#define SYS_CPU1_INT_32_63_STATUS_RESERVED3_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_TOUCHED_INT_ST_POS (20) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_TOUCHED_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_USBPLUG_INT_ST_POS (21) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_USBPLUG_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_RTC_INT_ST_POS (22) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_RTC_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_CPU1_GPIO_INT_ST_POS (23) 
#define SYS_CPU1_INT_32_63_STATUS_CPU1_GPIO_INT_ST_MASK (0x1) 

#define SYS_CPU1_INT_32_63_STATUS_RESERVED4_POS (24) 
#define SYS_CPU1_INT_32_63_STATUS_RESERVED4_MASK (0xFF) 

/* REG_0x30 */
#define SYS_GPIO_CONFIG0_ADDR  (SYS_LL_REG_BASE  + 0x30*4) //REG ADDR :0x440100c0
#define SYS_GPIO_CONFIG0_SYS_GPIO0_POS (0) 
#define SYS_GPIO_CONFIG0_SYS_GPIO0_MASK (0xF) 

#define SYS_GPIO_CONFIG0_SYS_GPIO1_POS (4) 
#define SYS_GPIO_CONFIG0_SYS_GPIO1_MASK (0xF) 

#define SYS_GPIO_CONFIG0_SYS_GPIO2_POS (8) 
#define SYS_GPIO_CONFIG0_SYS_GPIO2_MASK (0xF) 

#define SYS_GPIO_CONFIG0_SYS_GPIO3_POS (12) 
#define SYS_GPIO_CONFIG0_SYS_GPIO3_MASK (0xF) 

#define SYS_GPIO_CONFIG0_SYS_GPIO4_POS (16) 
#define SYS_GPIO_CONFIG0_SYS_GPIO4_MASK (0xF) 

#define SYS_GPIO_CONFIG0_SYS_GPIO5_POS (20) 
#define SYS_GPIO_CONFIG0_SYS_GPIO5_MASK (0xF) 

#define SYS_GPIO_CONFIG0_SYS_GPIO6_POS (24) 
#define SYS_GPIO_CONFIG0_SYS_GPIO6_MASK (0xF) 

#define SYS_GPIO_CONFIG0_SYS_GPIO7_POS (28) 
#define SYS_GPIO_CONFIG0_SYS_GPIO7_MASK (0xF) 

/* REG_0x31 */
#define SYS_GPIO_CONFIG1_ADDR  (SYS_LL_REG_BASE  + 0x31*4) //REG ADDR :0x440100c4
#define SYS_GPIO_CONFIG1_SYS_GPIO8_POS (0) 
#define SYS_GPIO_CONFIG1_SYS_GPIO8_MASK (0xF) 

#define SYS_GPIO_CONFIG1_SYS_GPIO9_POS (4) 
#define SYS_GPIO_CONFIG1_SYS_GPIO9_MASK (0xF) 

#define SYS_GPIO_CONFIG1_SYS_GPIO10_POS (8) 
#define SYS_GPIO_CONFIG1_SYS_GPIO10_MASK (0xF) 

#define SYS_GPIO_CONFIG1_SYS_GPIO11_POS (12) 
#define SYS_GPIO_CONFIG1_SYS_GPIO11_MASK (0xF) 

#define SYS_GPIO_CONFIG1_SYS_GPIO12_POS (16) 
#define SYS_GPIO_CONFIG1_SYS_GPIO12_MASK (0xF) 

#define SYS_GPIO_CONFIG1_SYS_GPIO13_POS (20) 
#define SYS_GPIO_CONFIG1_SYS_GPIO13_MASK (0xF) 

#define SYS_GPIO_CONFIG1_SYS_GPIO14_POS (24) 
#define SYS_GPIO_CONFIG1_SYS_GPIO14_MASK (0xF) 

#define SYS_GPIO_CONFIG1_SYS_GPIO15_POS (28) 
#define SYS_GPIO_CONFIG1_SYS_GPIO15_MASK (0xF) 

/* REG_0x32 */
#define SYS_GPIO_CONFIG2_ADDR  (SYS_LL_REG_BASE  + 0x32*4) //REG ADDR :0x440100c8
#define SYS_GPIO_CONFIG2_SYS_GPIO16_POS (0) 
#define SYS_GPIO_CONFIG2_SYS_GPIO16_MASK (0xF) 

#define SYS_GPIO_CONFIG2_SYS_GPIO17_POS (4) 
#define SYS_GPIO_CONFIG2_SYS_GPIO17_MASK (0xF) 

#define SYS_GPIO_CONFIG2_SYS_GPIO18_POS (8) 
#define SYS_GPIO_CONFIG2_SYS_GPIO18_MASK (0xF) 

#define SYS_GPIO_CONFIG2_SYS_GPIO19_POS (12) 
#define SYS_GPIO_CONFIG2_SYS_GPIO19_MASK (0xF) 

#define SYS_GPIO_CONFIG2_SYS_GPIO20_POS (16) 
#define SYS_GPIO_CONFIG2_SYS_GPIO20_MASK (0xF) 

#define SYS_GPIO_CONFIG2_SYS_GPIO21_POS (20) 
#define SYS_GPIO_CONFIG2_SYS_GPIO21_MASK (0xF) 

#define SYS_GPIO_CONFIG2_SYS_GPIO22_POS (24) 
#define SYS_GPIO_CONFIG2_SYS_GPIO22_MASK (0xF) 

#define SYS_GPIO_CONFIG2_SYS_GPIO23_POS (28) 
#define SYS_GPIO_CONFIG2_SYS_GPIO23_MASK (0xF) 

/* REG_0x33 */
#define SYS_GPIO_CONFIG3_ADDR  (SYS_LL_REG_BASE  + 0x33*4) //REG ADDR :0x440100cc
#define SYS_GPIO_CONFIG3_SYS_GPIO24_POS (0) 
#define SYS_GPIO_CONFIG3_SYS_GPIO24_MASK (0xF) 

#define SYS_GPIO_CONFIG3_SYS_GPIO25_POS (4) 
#define SYS_GPIO_CONFIG3_SYS_GPIO25_MASK (0xF) 

#define SYS_GPIO_CONFIG3_SYS_GPIO26_POS (8) 
#define SYS_GPIO_CONFIG3_SYS_GPIO26_MASK (0xF) 

#define SYS_GPIO_CONFIG3_SYS_GPIO27_POS (12) 
#define SYS_GPIO_CONFIG3_SYS_GPIO27_MASK (0xF) 

#define SYS_GPIO_CONFIG3_SYS_GPIO28_POS (16) 
#define SYS_GPIO_CONFIG3_SYS_GPIO28_MASK (0xF) 

#define SYS_GPIO_CONFIG3_SYS_GPIO29_POS (20) 
#define SYS_GPIO_CONFIG3_SYS_GPIO29_MASK (0xF) 

#define SYS_GPIO_CONFIG3_SYS_GPIO30_POS (24) 
#define SYS_GPIO_CONFIG3_SYS_GPIO30_MASK (0xF) 

#define SYS_GPIO_CONFIG3_SYS_GPIO31_POS (28) 
#define SYS_GPIO_CONFIG3_SYS_GPIO31_MASK (0xF) 

/* REG_0x34 */
#define SYS_GPIO_CONFIG4_ADDR  (SYS_LL_REG_BASE  + 0x34*4) //REG ADDR :0x440100d0
#define SYS_GPIO_CONFIG4_SYS_GPIO32_POS (0) 
#define SYS_GPIO_CONFIG4_SYS_GPIO32_MASK (0xF) 

#define SYS_GPIO_CONFIG4_SYS_GPIO33_POS (4) 
#define SYS_GPIO_CONFIG4_SYS_GPIO33_MASK (0xF) 

#define SYS_GPIO_CONFIG4_SYS_GPIO34_POS (8) 
#define SYS_GPIO_CONFIG4_SYS_GPIO34_MASK (0xF) 

#define SYS_GPIO_CONFIG4_SYS_GPIO35_POS (12) 
#define SYS_GPIO_CONFIG4_SYS_GPIO35_MASK (0xF) 

#define SYS_GPIO_CONFIG4_SYS_GPIO36_POS (16) 
#define SYS_GPIO_CONFIG4_SYS_GPIO36_MASK (0xF) 

#define SYS_GPIO_CONFIG4_SYS_GPIO37_POS (20) 
#define SYS_GPIO_CONFIG4_SYS_GPIO37_MASK (0xF) 

#define SYS_GPIO_CONFIG4_SYS_GPIO38_POS (24) 
#define SYS_GPIO_CONFIG4_SYS_GPIO38_MASK (0xF) 

#define SYS_GPIO_CONFIG4_SYS_GPIO39_POS (28) 
#define SYS_GPIO_CONFIG4_SYS_GPIO39_MASK (0xF) 

/* REG_0x35 */
#define SYS_GPIO_CONFIG5_ADDR  (SYS_LL_REG_BASE  + 0x35*4) //REG ADDR :0x440100d4
#define SYS_GPIO_CONFIG5_SYS_GPIO40_POS (0) 
#define SYS_GPIO_CONFIG5_SYS_GPIO40_MASK (0xF) 

#define SYS_GPIO_CONFIG5_SYS_GPIO41_POS (4) 
#define SYS_GPIO_CONFIG5_SYS_GPIO41_MASK (0xF) 

#define SYS_GPIO_CONFIG5_SYS_GPIO42_POS (8) 
#define SYS_GPIO_CONFIG5_SYS_GPIO42_MASK (0xF) 

#define SYS_GPIO_CONFIG5_SYS_GPIO43_POS (12) 
#define SYS_GPIO_CONFIG5_SYS_GPIO43_MASK (0xF) 

#define SYS_GPIO_CONFIG5_SYS_GPIO44_POS (16) 
#define SYS_GPIO_CONFIG5_SYS_GPIO44_MASK (0xF) 

#define SYS_GPIO_CONFIG5_SYS_GPIO45_POS (20) 
#define SYS_GPIO_CONFIG5_SYS_GPIO45_MASK (0xF) 

#define SYS_GPIO_CONFIG5_SYS_GPIO46_POS (24) 
#define SYS_GPIO_CONFIG5_SYS_GPIO46_MASK (0xF) 

#define SYS_GPIO_CONFIG5_SYS_GPIO47_POS (28) 
#define SYS_GPIO_CONFIG5_SYS_GPIO47_MASK (0xF) 

/* REG_0x38 */
#define SYS_SYS_DEBUG_CONFIG0_ADDR  (SYS_LL_REG_BASE  + 0x38*4) //REG ADDR :0x440100e0
#define SYS_SYS_DEBUG_CONFIG0_DBUG_CONFIG0_POS (0) 
#define SYS_SYS_DEBUG_CONFIG0_DBUG_CONFIG0_MASK (0xFFFFFFFF) 

/* REG_0x39 */
#define SYS_SYS_DEBUG_CONFIG1_ADDR  (SYS_LL_REG_BASE  + 0x39*4) //REG ADDR :0x440100e4
#define SYS_SYS_DEBUG_CONFIG1_DBUG_CONFIG1_POS (0) 
#define SYS_SYS_DEBUG_CONFIG1_DBUG_CONFIG1_MASK (0xFFFFFFFF) 

/* REG_0x40 */
#define SYS_ANA_REG0_ADDR  (SYS_LL_REG_BASE  + 0x40*4) //REG ADDR :0x44010100
#define SYS_ANA_REG0_CK2652SEL_POS (0) 
#define SYS_ANA_REG0_CK2652SEL_MASK (0x1) 

#define SYS_ANA_REG0_CP_POS (1) 
#define SYS_ANA_REG0_CP_MASK (0x7) 

#define SYS_ANA_REG0_SPIDETEN_POS (4) 
#define SYS_ANA_REG0_SPIDETEN_MASK (0x1) 

#define SYS_ANA_REG0_HVREF_POS (5) 
#define SYS_ANA_REG0_HVREF_MASK (0x3) 

#define SYS_ANA_REG0_LVREF_POS (7) 
#define SYS_ANA_REG0_LVREF_MASK (0x3) 

#define SYS_ANA_REG0_RZCTRL26M_POS (9) 
#define SYS_ANA_REG0_RZCTRL26M_MASK (0x1) 

#define SYS_ANA_REG0_LOOPRZCTRL_POS (10) 
#define SYS_ANA_REG0_LOOPRZCTRL_MASK (0xF) 

#define SYS_ANA_REG0_RPC_POS (14) 
#define SYS_ANA_REG0_RPC_MASK (0x3) 

#define SYS_ANA_REG0_NSYN_POS (16) 
#define SYS_ANA_REG0_NSYN_MASK (0x1) 

#define SYS_ANA_REG0_CKSEL_POS (17) 
#define SYS_ANA_REG0_CKSEL_MASK (0x3) 

#define SYS_ANA_REG0_SPITRIG_POS (19) 
#define SYS_ANA_REG0_SPITRIG_MASK (0x1) 

#define SYS_ANA_REG0_BAND_POS (20) 
#define SYS_ANA_REG0_BAND_MASK (0x1F) 

#define SYS_ANA_REG0_BANDMANUAL_POS (25) 
#define SYS_ANA_REG0_BANDMANUAL_MASK (0x1) 

#define SYS_ANA_REG0_DSPTRIG_POS (26) 
#define SYS_ANA_REG0_DSPTRIG_MASK (0x1) 

#define SYS_ANA_REG0_LPEN_DPLL_POS (27) 
#define SYS_ANA_REG0_LPEN_DPLL_MASK (0x1) 

#define SYS_ANA_REG0_XAMP_POS (28) 
#define SYS_ANA_REG0_XAMP_MASK (0xF) 

/* REG_0x41 */
#define SYS_ANA_REG1_ADDR  (SYS_LL_REG_BASE  + 0x41*4) //REG ADDR :0x44010104
#define SYS_ANA_REG1_NC_POS (0) 
#define SYS_ANA_REG1_NC_MASK (0x1) 

#define SYS_ANA_REG1_DPLL_VREFSEL_POS (1) 
#define SYS_ANA_REG1_DPLL_VREFSEL_MASK (0x1) 

#define SYS_ANA_REG1_MSW_POS (2) 
#define SYS_ANA_REG1_MSW_MASK (0x1FF) 

#define SYS_ANA_REG1_ICTRL_POS (11) 
#define SYS_ANA_REG1_ICTRL_MASK (0x7) 

#define SYS_ANA_REG1_OSC_TRIG_POS (14) 
#define SYS_ANA_REG1_OSC_TRIG_MASK (0x1) 

#define SYS_ANA_REG1_OSCCAL_TRIG_POS (15) 
#define SYS_ANA_REG1_OSCCAL_TRIG_MASK (0x1) 

#define SYS_ANA_REG1_CNTI_POS (16) 
#define SYS_ANA_REG1_CNTI_MASK (0x1FF) 

#define SYS_ANA_REG1_SPI_RST_POS (25) 
#define SYS_ANA_REG1_SPI_RST_MASK (0x1) 

#define SYS_ANA_REG1_AMSEL_POS (26) 
#define SYS_ANA_REG1_AMSEL_MASK (0x1) 

#define SYS_ANA_REG1_DIVCTRL_POS (27) 
#define SYS_ANA_REG1_DIVCTRL_MASK (0x7) 

#define SYS_ANA_REG1_DCO_TSTEN_POS (30) 
#define SYS_ANA_REG1_DCO_TSTEN_MASK (0x1) 

#define SYS_ANA_REG1_ROSC_TSTEN_POS (31) 
#define SYS_ANA_REG1_ROSC_TSTEN_MASK (0x1) 

/* REG_0x42 */
#define SYS_ANA_REG2_ADDR  (SYS_LL_REG_BASE  + 0x42*4) //REG ADDR :0x44010108
#define SYS_ANA_REG2_PWMSCMEN_POS (0) 
#define SYS_ANA_REG2_PWMSCMEN_MASK (0x1) 

#define SYS_ANA_REG2_BUCK_FASTEN_POS (1) 
#define SYS_ANA_REG2_BUCK_FASTEN_MASK (0x1) 

#define SYS_ANA_REG2_CLS_POS (2) 
#define SYS_ANA_REG2_CLS_MASK (0x7) 

#define SYS_ANA_REG2_PFMS_POS (5) 
#define SYS_ANA_REG2_PFMS_MASK (0x1F) 

#define SYS_ANA_REG2_RIPC_POS (10) 
#define SYS_ANA_REG2_RIPC_MASK (0x7) 

#define SYS_ANA_REG2_RAMPC_POS (13) 
#define SYS_ANA_REG2_RAMPC_MASK (0xF) 

#define SYS_ANA_REG2_RAMPCEN_POS (17) 
#define SYS_ANA_REG2_RAMPCEN_MASK (0x1) 

#define SYS_ANA_REG2_DPFMEN_POS (18) 
#define SYS_ANA_REG2_DPFMEN_MASK (0x1) 

#define SYS_ANA_REG2_PFMEN_POS (19) 
#define SYS_ANA_REG2_PFMEN_MASK (0x1) 

#define SYS_ANA_REG2_FORCEPFM_POS (20) 
#define SYS_ANA_REG2_FORCEPFM_MASK (0x1) 

#define SYS_ANA_REG2_SWRSTEN_POS (21) 
#define SYS_ANA_REG2_SWRSTEN_MASK (0x1) 

#define SYS_ANA_REG2_TMPOSEL_POS (22) 
#define SYS_ANA_REG2_TMPOSEL_MASK (0x3) 

#define SYS_ANA_REG2_MPOEN_POS (24) 
#define SYS_ANA_REG2_MPOEN_MASK (0x1) 

#define SYS_ANA_REG2_SPI_LATCHB_POS (25) 
#define SYS_ANA_REG2_SPI_LATCHB_MASK (0x1) 

#define SYS_ANA_REG2_LDOSEL_POS (26) 
#define SYS_ANA_REG2_LDOSEL_MASK (0x1) 

#define SYS_ANA_REG2_IOVOC_POS (27) 
#define SYS_ANA_REG2_IOVOC_MASK (0x7) 

#define SYS_ANA_REG2_VBPBUF_HP_POS (30) 
#define SYS_ANA_REG2_VBPBUF_HP_MASK (0x1) 

#define SYS_ANA_REG2_BYPASSEN_POS (31) 
#define SYS_ANA_REG2_BYPASSEN_MASK (0x1) 

/* REG_0x43 */
#define SYS_ANA_REG3_ADDR  (SYS_LL_REG_BASE  + 0x43*4) //REG ADDR :0x4401010c
#define SYS_ANA_REG3_ZCDTA_POS (0) 
#define SYS_ANA_REG3_ZCDTA_MASK (0x1F) 

#define SYS_ANA_REG3_ZCDCALA_POS (5) 
#define SYS_ANA_REG3_ZCDCALA_MASK (0x3F) 

#define SYS_ANA_REG3_ZCDMEN_POS (11) 
#define SYS_ANA_REG3_ZCDMEN_MASK (0x1) 

#define SYS_ANA_REG3_ZCDCALEN_POS (12) 
#define SYS_ANA_REG3_ZCDCALEN_MASK (0x1) 

#define SYS_ANA_REG3_ZCDCAL_TRI_POS (13) 
#define SYS_ANA_REG3_ZCDCAL_TRI_MASK (0x1) 

#define SYS_ANA_REG3_MROSCSEL_POS (14) 
#define SYS_ANA_REG3_MROSCSEL_MASK (0x1) 

#define SYS_ANA_REG3_MFSEL_POS (15) 
#define SYS_ANA_REG3_MFSEL_MASK (0x7) 

#define SYS_ANA_REG3_MROSCBCAL_POS (18) 
#define SYS_ANA_REG3_MROSCBCAL_MASK (0xF) 

#define SYS_ANA_REG3_OSCCALTRIG_POS (22) 
#define SYS_ANA_REG3_OSCCALTRIG_MASK (0x1) 

#define SYS_ANA_REG3_CKINTSEL_POS (23) 
#define SYS_ANA_REG3_CKINTSEL_MASK (0x1) 

#define SYS_ANA_REG3_CKFS_POS (24) 
#define SYS_ANA_REG3_CKFS_MASK (0x3) 

#define SYS_ANA_REG3_VLSEL_LDODIG_POS (26) 
#define SYS_ANA_REG3_VLSEL_LDODIG_MASK (0x7) 

#define SYS_ANA_REG3_VHSEL_LDODIG_POS (29) 
#define SYS_ANA_REG3_VHSEL_LDODIG_MASK (0x7) 

/* REG_0x44 */
#define SYS_ANA_REG4_ADDR  (SYS_LL_REG_BASE  + 0x44*4) //REG ADDR :0x44010110
#define SYS_ANA_REG4_NC_POS (0) 
#define SYS_ANA_REG4_NC_MASK (0x1F) 

#define SYS_ANA_REG4_CB_MANU_VAL_POS (5) 
#define SYS_ANA_REG4_CB_MANU_VAL_MASK (0x1F) 

#define SYS_ANA_REG4_CB_CAL_TRIG_POS (10) 
#define SYS_ANA_REG4_CB_CAL_TRIG_MASK (0x1) 

#define SYS_ANA_REG4_CB_CAL_MANU_POS (11) 
#define SYS_ANA_REG4_CB_CAL_MANU_MASK (0x1) 

#define SYS_ANA_REG4_ROSC_CAL_INTVAL_POS (12) 
#define SYS_ANA_REG4_ROSC_CAL_INTVAL_MASK (0x7) 

#define SYS_ANA_REG4_MANU_CIN_POS (15) 
#define SYS_ANA_REG4_MANU_CIN_MASK (0x7F) 

#define SYS_ANA_REG4_MANU_FIN_POS (22) 
#define SYS_ANA_REG4_MANU_FIN_MASK (0x1F) 

#define SYS_ANA_REG4_ROSC_CAL_MODE_POS (27) 
#define SYS_ANA_REG4_ROSC_CAL_MODE_MASK (0x1) 

#define SYS_ANA_REG4_ROSC_CAL_TRIG_POS (28) 
#define SYS_ANA_REG4_ROSC_CAL_TRIG_MASK (0x1) 

#define SYS_ANA_REG4_ROSC_CAL_EN_POS (29) 
#define SYS_ANA_REG4_ROSC_CAL_EN_MASK (0x1) 

#define SYS_ANA_REG4_ROSC_MANU_EN_POS (30) 
#define SYS_ANA_REG4_ROSC_MANU_EN_MASK (0x1) 

#define SYS_ANA_REG4_ROSC_TSTEN_POS (31) 
#define SYS_ANA_REG4_ROSC_TSTEN_MASK (0x1) 

/* REG_0x45 */
#define SYS_ANA_REG5_ADDR  (SYS_LL_REG_BASE  + 0x45*4) //REG ADDR :0x44010114
#define SYS_ANA_REG5_VREF_SCALE_POS (0) 
#define SYS_ANA_REG5_VREF_SCALE_MASK (0x1) 

#define SYS_ANA_REG5_DCCAL_EN_POS (1) 
#define SYS_ANA_REG5_DCCAL_EN_MASK (0x1) 

#define SYS_ANA_REG5_XTALH_CTUNE_POS (2) 
#define SYS_ANA_REG5_XTALH_CTUNE_MASK (0x7F) 

#define SYS_ANA_REG5_CKTST_SEL_POS (9) 
#define SYS_ANA_REG5_CKTST_SEL_MASK (0x3) 

#define SYS_ANA_REG5_CK_TST_ENBALE_POS (11) 
#define SYS_ANA_REG5_CK_TST_ENBALE_MASK (0x1) 

#define SYS_ANA_REG5_TRXT_TST_ENABLE_POS (12) 
#define SYS_ANA_REG5_TRXT_TST_ENABLE_MASK (0x1) 

#define SYS_ANA_REG5_ENCB_POS (13) 
#define SYS_ANA_REG5_ENCB_MASK (0x1) 

#define SYS_ANA_REG5_VCTRL_DPLLLDO_POS (14) 
#define SYS_ANA_REG5_VCTRL_DPLLLDO_MASK (0x3) 

#define SYS_ANA_REG5_VCTRL_SYSLDO_POS (16) 
#define SYS_ANA_REG5_VCTRL_SYSLDO_MASK (0x3) 

#define SYS_ANA_REG5_TEMPTST_EN_POS (18) 
#define SYS_ANA_REG5_TEMPTST_EN_MASK (0x1) 


#define SYS_ANA_REG5_GADC_TSEL_POS (19) 
#define SYS_ANA_REG5_GADC_TSEL_MASK (0x7) 

#define SYS_ANA_REG5_GADC_INBUF_ICTRL_POS (19) 
#define SYS_ANA_REG5_GADC_INBUF_ICTRL_MASK (0x3) 

#define SYS_ANA_REG5_NC_POS (21) 
#define SYS_ANA_REG5_NC_MASK (0x1) 


#define SYS_ANA_REG5_XTALH_ICTRL_POS (22) 
#define SYS_ANA_REG5_XTALH_ICTRL_MASK (0x1) 

#define SYS_ANA_REG5_BGCALM_POS (23) 
#define SYS_ANA_REG5_BGCALM_MASK (0x3F) 

#define SYS_ANA_REG5_BGCAL_TRIG_POS (29) 
#define SYS_ANA_REG5_BGCAL_TRIG_MASK (0x1) 

#define SYS_ANA_REG5_BGCAL_MANU_POS (30) 
#define SYS_ANA_REG5_BGCAL_MANU_MASK (0x1) 

#define SYS_ANA_REG5_BGCAL_EN_POS (31) 
#define SYS_ANA_REG5_BGCAL_EN_MASK (0x1) 

/* REG_0x46 */
#define SYS_ANA_REG6_ADDR  (SYS_LL_REG_BASE  + 0x46*4) //REG ADDR :0x44010118
#define SYS_ANA_REG6_ITUNE_XTALL_POS (0) 
#define SYS_ANA_REG6_ITUNE_XTALL_MASK (0xF) 

#define SYS_ANA_REG6_XTALL_TEN_POS (4) 
#define SYS_ANA_REG6_XTALL_TEN_MASK (0x1) 

#define SYS_ANA_REG6_PSLDO_VSEL_POS (5) 
#define SYS_ANA_REG6_PSLDO_VSEL_MASK (0x1) 

#define SYS_ANA_REG6_EN_USB_POS (6) 
#define SYS_ANA_REG6_EN_USB_MASK (0x1) 

#define SYS_ANA_REG6_EN_XTALL_POS (7) 
#define SYS_ANA_REG6_EN_XTALL_MASK (0x1) 

#define SYS_ANA_REG6_EN_DCO_POS (8) 
#define SYS_ANA_REG6_EN_DCO_MASK (0x1) 

#define SYS_ANA_REG6_EN_PSRAM_LDO_POS (9) 
#define SYS_ANA_REG6_EN_PSRAM_LDO_MASK (0x1) 

#define SYS_ANA_REG6_EN_TEMPDET_POS (10) 
#define SYS_ANA_REG6_EN_TEMPDET_MASK (0x1) 

#define SYS_ANA_REG6_EN_AUDPLL_POS (11) 
#define SYS_ANA_REG6_EN_AUDPLL_MASK (0x1) 

#define SYS_ANA_REG6_EN_DPLL_POS (12) 
#define SYS_ANA_REG6_EN_DPLL_MASK (0x1) 

#define SYS_ANA_REG6_EN_SYSLDO_POS (13) 
#define SYS_ANA_REG6_EN_SYSLDO_MASK (0x1) 

#define SYS_ANA_REG6_EN_AUD_POS (14) 
#define SYS_ANA_REG6_EN_AUD_MASK (0x1)

#define SYS_ANA_REG6_PWD_GADC_BUF_POS (15) 
#define SYS_ANA_REG6_PWD_GADC_BUF_MASK (0x1) 

#define SYS_ANA_REG6_NC_POS (16) 
#define SYS_ANA_REG6_NC_MASK (0x1) 

#define SYS_ANA_REG6_VAON_SEL_POS (17) 
#define SYS_ANA_REG6_VAON_SEL_MASK (0x1)

#define SYS_ANA_REG6_XTAL_HPSRR_EN_POS (18) 
#define SYS_ANA_REG6_XTAL_HPSRR_EN_MASK (0x1) 

#define SYS_ANA_REG6_EN_XTAL2RF_POS (19) 
#define SYS_ANA_REG6_EN_XTAL2RF_MASK (0x1) 

#define SYS_ANA_REG6_EN_SLEEP_POS (20) 
#define SYS_ANA_REG6_EN_SLEEP_MASK (0x1) 

#define SYS_ANA_REG6_CLKBUF_HD_POS (21) 
#define SYS_ANA_REG6_CLKBUF_HD_MASK (0x1) 

#define SYS_ANA_REG6_CLKBUF_DSEL_MANU_POS (22) 
#define SYS_ANA_REG6_CLKBUF_DSEL_MANU_MASK (0x1) 

#define SYS_ANA_REG6_XTAL_LPMODE_CTRL_POS (23) 
#define SYS_ANA_REG6_XTAL_LPMODE_CTRL_MASK (0x1) 

#define SYS_ANA_REG6_RXTAL_LP_POS (24) 
#define SYS_ANA_REG6_RXTAL_LP_MASK (0xF) 

#define SYS_ANA_REG6_RXTAL_HP_POS (28) 
#define SYS_ANA_REG6_RXTAL_HP_MASK (0xF) 

/* REG_0x47 */
#define SYS_ANA_REG7_ADDR  (SYS_LL_REG_BASE  + 0x47*4) //REG ADDR :0x4401011c
#define SYS_ANA_REG7_RNG_TSTCK_SEL_POS (0) 
#define SYS_ANA_REG7_RNG_TSTCK_SEL_MASK (0x1) 

#define SYS_ANA_REG7_RNG_TSTEN_POS (1) 
#define SYS_ANA_REG7_RNG_TSTEN_MASK (0x1) 

#define SYS_ANA_REG7_ITUNE_REF_POS (2) 
#define SYS_ANA_REG7_ITUNE_REF_MASK (0x7) 

#define SYS_ANA_REG7_ITUNE_OPA_POS (5) 
#define SYS_ANA_REG7_ITUNE_OPA_MASK (0x7) 

#define SYS_ANA_REG7_ITUNE_CMP_POS (8) 
#define SYS_ANA_REG7_ITUNE_CMP_MASK (0x7) 

#define SYS_ANA_REG7_RNOOISE_SEL_POS (11) 
#define SYS_ANA_REG7_RNOOISE_SEL_MASK (0x1) 

#define SYS_ANA_REG7_FSLOW_SEL_POS (12) 
#define SYS_ANA_REG7_FSLOW_SEL_MASK (0x7) 

#define SYS_ANA_REG7_FFAST_SEL_POS (15) 
#define SYS_ANA_REG7_FFAST_SEL_MASK (0xF) 

#define SYS_ANA_REG7_GADC_CAL_SEL_POS (19) 
#define SYS_ANA_REG7_GADC_CAL_SEL_MASK (0x3) 

#define SYS_ANA_REG7_GADC_TEN_POS (21) 
#define SYS_ANA_REG7_GADC_TEN_MASK (0x1) 

#define SYS_ANA_REG7_NC_POS (21) 
#define SYS_ANA_REG7_NC_MASK (0x1) 

#define SYS_ANA_REG7_GADC_CMP_ICTRL_POS (22) 
#define SYS_ANA_REG7_GADC_CMP_ICTRL_MASK (0xF) 

#define SYS_ANA_REG7_GADC_BUF_ICTRL_POS (26) 
#define SYS_ANA_REG7_GADC_BUF_ICTRL_MASK (0xF) 

#define SYS_ANA_REG7_VREF_SEL_POS (30) 
#define SYS_ANA_REG7_VREF_SEL_MASK (0x1) 

#define SYS_ANA_REG7_SCAL_EN_POS (31) 
#define SYS_ANA_REG7_SCAL_EN_MASK (0x1) 

/* REG_0x48 */
#define SYS_ANA_REG8_ADDR  (SYS_LL_REG_BASE  + 0x48*4) //REG ADDR :0x44010120
#define SYS_ANA_REG8_CAP_CALSPI_POS (0) 
#define SYS_ANA_REG8_CAP_CALSPI_MASK (0x1FF) 

#define SYS_ANA_REG8_GAIN_S_POS (9) 
#define SYS_ANA_REG8_GAIN_S_MASK (0x3) 

#define SYS_ANA_REG8_PWD_TD_POS (11) 
#define SYS_ANA_REG8_PWD_TD_MASK (0x1) 

#define SYS_ANA_REG8_EN_FSR_POS (12) 
#define SYS_ANA_REG8_EN_FSR_MASK (0x1) 

#define SYS_ANA_REG8_EN_SCM_POS (13) 
#define SYS_ANA_REG8_EN_SCM_MASK (0x1) 

#define SYS_ANA_REG8_EN_ADCMODE_POS (14) 
#define SYS_ANA_REG8_EN_ADCMODE_MASK (0x1) 

#define SYS_ANA_REG8_EN_LPMODE_POS (15) 
#define SYS_ANA_REG8_EN_LPMODE_MASK (0x1) 

#define SYS_ANA_REG8_CHS_SCAN_POS (16) 
#define SYS_ANA_REG8_CHS_SCAN_MASK (0xFFFF) 

/* REG_0x49 */
#define SYS_ANA_REG9_ADDR  (SYS_LL_REG_BASE  + 0x49*4) //REG ADDR :0x44010124
#define SYS_ANA_REG9_EN_OTP_SPI_POS (0) 
#define SYS_ANA_REG9_EN_OTP_SPI_MASK (0x1) 

#define SYS_ANA_REG9_NC3_POS (1) 
#define SYS_ANA_REG9_NC3_MASK (0x7FF) 

#define SYS_ANA_REG9_NC2_POS (12) 
#define SYS_ANA_REG9_NC2_MASK (0x1) 

#define SYS_ANA_REG9_DIGOVR_EN_POS (13) 
#define SYS_ANA_REG9_DIGOVR_EN_MASK (0x1) 

#define SYS_ANA_REG9_ENTEMP2_POS (1) 
#define SYS_ANA_REG9_ENTEMP2_MASK (0x1) 

#define SYS_ANA_REG9_VTEMPSEL_POS (2) 
#define SYS_ANA_REG9_VTEMPSEL_MASK (0x3) 

#define SYS_ANA_REG9_VTSEL_POS (4) 
#define SYS_ANA_REG9_VTSEL_MASK (0x1) 

#define SYS_ANA_REG9_EN_BIAS_5U_POS (5) 
#define SYS_ANA_REG9_EN_BIAS_5U_MASK (0x1) 

#define SYS_ANA_REG9_DUMMY2_POS (6) 
#define SYS_ANA_REG9_DUMMY2_MASK (0x1) 

#define SYS_ANA_REG9_TOUCH_SERIAL_CAP_POS (7) 
#define SYS_ANA_REG9_TOUCH_SERIAL_CAP_MASK (0x1) 

#define SYS_ANA_REG9_BUCKFB_CZENB_POS (8) 
#define SYS_ANA_REG9_BUCKFB_CZENB_MASK (0x1) 

#define SYS_ANA_REG9_BUCKEA_CUR_CTRL_POS (9) 
#define SYS_ANA_REG9_BUCKEA_CUR_CTRL_MASK (0x3) 

#define SYS_ANA_REG9_CBTST_EN_POS (11) 
#define SYS_ANA_REG9_CBTST_EN_MASK (0x1) 

#define SYS_ANA_REG9_PSLDO_VSEL_POS (12) 
#define SYS_ANA_REG9_PSLDO_VSEL_MASK (0x1) 

#define SYS_ANA_REG9_OVR_L_POS (13) 
#define SYS_ANA_REG9_OVR_L_MASK (0x1)

#define SYS_ANA_REG9_USBPEN_POS (14) 
#define SYS_ANA_REG9_USBPEN_MASK (0xF) 

#define SYS_ANA_REG9_USBNEN_POS (18) 
#define SYS_ANA_REG9_USBNEN_MASK (0xF) 

#define SYS_ANA_REG9_USB_SPEED_POS (22) 
#define SYS_ANA_REG9_USB_SPEED_MASK (0x1) 

#define SYS_ANA_REG9_USB_DEEPSLEEP_POS (23) 
#define SYS_ANA_REG9_USB_DEEPSLEEP_MASK (0x1) 

#define SYS_ANA_REG9_MAN_MODE_POS (24) 
#define SYS_ANA_REG9_MAN_MODE_MASK (0x1) 

#define SYS_ANA_REG9_CRG_POS (25) 
#define SYS_ANA_REG9_CRG_MASK (0x3) 

#define SYS_ANA_REG9_VREFS_POS (27) 
#define SYS_ANA_REG9_VREFS_MASK (0x7) 

#define SYS_ANA_REG9_NC1_POS (30) 
#define SYS_ANA_REG9_NC1_MASK (0x1) 

#define SYS_ANA_REG9_EN_CAL_POS (31) 
#define SYS_ANA_REG9_EN_CAL_MASK (0x1) 

/* REG_0x4A */
#define SYS_ANA_REG10_ADDR  (SYS_LL_REG_BASE  + 0x4A*4) //REG ADDR :0x44010128
#define SYS_ANA_REG10_SDM_VAL_POS (0) 
#define SYS_ANA_REG10_SDM_VAL_MASK (0x3FFFFFFF) 

#define SYS_ANA_REG10_VCO_HFREQ_ENB_POS (30) 
#define SYS_ANA_REG10_VCO_HFREQ_ENB_MASK (0x1) 

#define SYS_ANA_REG10_CAL_REFEN_POS (31) 
#define SYS_ANA_REG10_CAL_REFEN_MASK (0x1) 

/* REG_0x4B */
#define SYS_ANA_REG11_ADDR  (SYS_LL_REG_BASE  + 0x4B*4) //REG ADDR :0x4401012c
#define SYS_ANA_REG11_INT_MOD_POS (0) 
#define SYS_ANA_REG11_INT_MOD_MASK (0x1) 

#define SYS_ANA_REG11_NSYN_POS (1) 
#define SYS_ANA_REG11_NSYN_MASK (0x1) 

#define SYS_ANA_REG11_OPEN_ENB_POS (2) 
#define SYS_ANA_REG11_OPEN_ENB_MASK (0x1) 

#define SYS_ANA_REG11_RESET_POS (3) 
#define SYS_ANA_REG11_RESET_MASK (0x1) 

#define SYS_ANA_REG11_IOFFSET_POS (4) 
#define SYS_ANA_REG11_IOFFSET_MASK (0x7) 

#define SYS_ANA_REG11_LPFRZ_POS (7) 
#define SYS_ANA_REG11_LPFRZ_MASK (0xF) 

#define SYS_ANA_REG11_VSEL_POS (11) 
#define SYS_ANA_REG11_VSEL_MASK (0x7) 

#define SYS_ANA_REG11_VSEL_CAL_POS (14) 
#define SYS_ANA_REG11_VSEL_CAL_MASK (0x1) 

#define SYS_ANA_REG11_PWD_LOCKDET_POS (15) 
#define SYS_ANA_REG11_PWD_LOCKDET_MASK (0x1) 

#define SYS_ANA_REG11_LOCKDET_BYPASS_POS (16) 
#define SYS_ANA_REG11_LOCKDET_BYPASS_MASK (0x1) 

#define SYS_ANA_REG11_CKREF_LOOP_SEL_POS (17) 
#define SYS_ANA_REG11_CKREF_LOOP_SEL_MASK (0x1) 

#define SYS_ANA_REG11_SPI_TRIGGER_POS (18) 
#define SYS_ANA_REG11_SPI_TRIGGER_MASK (0x1) 

#define SYS_ANA_REG11_MANUAL_POS (19) 
#define SYS_ANA_REG11_MANUAL_MASK (0x1) 

#define SYS_ANA_REG11_TEST_EN_POS (20) 
#define SYS_ANA_REG11_TEST_EN_MASK (0x1) 

#define SYS_ANA_REG11_NC_POS (21) 
#define SYS_ANA_REG11_NC_MASK (0x1) 

#define SYS_ANA_REG11_ICP_POS (22) 
#define SYS_ANA_REG11_ICP_MASK (0x3) 

#define SYS_ANA_REG11_CK26MEN_POS (24) 
#define SYS_ANA_REG11_CK26MEN_MASK (0x1) 

#define SYS_ANA_REG11_CKAUDIO_OUTEN_POS (25) 
#define SYS_ANA_REG11_CKAUDIO_OUTEN_MASK (0x1) 

#define SYS_ANA_REG11_DIVCTRL_POS (26) 
#define SYS_ANA_REG11_DIVCTRL_MASK (0x7) 

#define SYS_ANA_REG11_CKSEL_POS (29) 
#define SYS_ANA_REG11_CKSEL_MASK (0x1) 

#define SYS_ANA_REG11_CK2MCU_POS (30) 
#define SYS_ANA_REG11_CK2MCU_MASK (0x1) 

#define SYS_ANA_REG11_AUDIOEN_POS (31) 
#define SYS_ANA_REG11_AUDIOEN_MASK (0x1) 

/* REG_0x4C */
#define SYS_ANA_REG12_ADDR  (SYS_LL_REG_BASE  + 0x4C*4) //REG ADDR :0x44010130
#define SYS_ANA_REG12_NC_POS (0) 
#define SYS_ANA_REG12_NC_MASK (0x3) 

#define SYS_ANA_REG12_DIGMIC_CKINV_POS (2) 
#define SYS_ANA_REG12_DIGMIC_CKINV_MASK (0x1) 

#define SYS_ANA_REG12_ENMICDIG_POS (3) 
#define SYS_ANA_REG12_ENMICDIG_MASK (0x1) 

#define SYS_ANA_REG12_AUDCK_RLCEN_POS (4) 
#define SYS_ANA_REG12_AUDCK_RLCEN_MASK (0x1) 

#define SYS_ANA_REG12_LCHCKINVEN_POS (5) 
#define SYS_ANA_REG12_LCHCKINVEN_MASK (0x1) 

#define SYS_ANA_REG12_LDO1V_VSEL1V_POS (6) 
#define SYS_ANA_REG12_LDO1V_VSEL1V_MASK (0x7) 

#define SYS_ANA_REG12_LDO1V_ADJ_POS (9) 
#define SYS_ANA_REG12_LDO1V_ADJ_MASK (0x1F) 

#define SYS_ANA_REG12_AUDVDD_TRM1V_POS (14) 
#define SYS_ANA_REG12_AUDVDD_TRM1V_MASK (0x3) 

#define SYS_ANA_REG12_AUDVDD_VOC1V_POS (16) 
#define SYS_ANA_REG12_AUDVDD_VOC1V_MASK (0x1F) 

#define SYS_ANA_REG12_ENAUDVDD1V_POS (21) 
#define SYS_ANA_REG12_ENAUDVDD1V_MASK (0x1) 

#define SYS_ANA_REG12_LOADHP_POS (22) 
#define SYS_ANA_REG12_LOADHP_MASK (0x1) 

#define SYS_ANA_REG12_ENAUDVDD1V5_POS (23) 
#define SYS_ANA_REG12_ENAUDVDD1V5_MASK (0x1) 

#define SYS_ANA_REG12_ENMICBIAS1V_POS (24) 
#define SYS_ANA_REG12_ENMICBIAS1V_MASK (0x1) 

#define SYS_ANA_REG12_MICBIAS_TRIM_POS (25) 
#define SYS_ANA_REG12_MICBIAS_TRIM_MASK (0x3) 

#define SYS_ANA_REG12_MICBIAS_VOC1V_POS (27) 
#define SYS_ANA_REG12_MICBIAS_VOC1V_MASK (0x1F) 

/* REG_0x4D */
#define SYS_ANA_REG13_ADDR  (SYS_LL_REG_BASE  + 0x4D*4) //REG ADDR :0x44010134
#define SYS_ANA_REG13_NC5_POS (0) 
#define SYS_ANA_REG13_NC5_MASK (0xFF) 

#define SYS_ANA_REG13_BYP_DWAADC_POS (8) 
#define SYS_ANA_REG13_BYP_DWAADC_MASK (0x1) 

#define SYS_ANA_REG13_RST_POS (9) 
#define SYS_ANA_REG13_RST_MASK (0x1) 

#define SYS_ANA_REG13_ADCDWA_MODE_POS (10) 
#define SYS_ANA_REG13_ADCDWA_MODE_MASK (0x1) 

#define SYS_ANA_REG13_VODADJSPI_POS (11) 
#define SYS_ANA_REG13_VODADJSPI_MASK (0x1F) 

#define SYS_ANA_REG13_NC4_POS (16) 
#define SYS_ANA_REG13_NC4_MASK (0x1F) 

#define SYS_ANA_REG13_REFVSEL_POS (21) 
#define SYS_ANA_REG13_REFVSEL_MASK (0x1) 

#define SYS_ANA_REG13_NC3_POS (22) 
#define SYS_ANA_REG13_NC3_MASK (0x1) 

#define SYS_ANA_REG13_CAPSW1V_POS (23) 
#define SYS_ANA_REG13_CAPSW1V_MASK (0x1F) 

#define SYS_ANA_REG13_NC2_POS (28) 
#define SYS_ANA_REG13_NC2_MASK (0x3) 

#define SYS_ANA_REG13_ADCCKINVEN_POS (30) 
#define SYS_ANA_REG13_ADCCKINVEN_MASK (0x1) 

#define SYS_ANA_REG13_NC1_POS (31) 
#define SYS_ANA_REG13_NC1_MASK (0x1) 

/* REG_0x4E */
#define SYS_ANA_REG14_ADDR  (SYS_LL_REG_BASE  + 0x4E*4) //REG ADDR :0x44010138
#define SYS_ANA_REG14_ISEL_POS (0) 
#define SYS_ANA_REG14_ISEL_MASK (0x3) 

#define SYS_ANA_REG14_MICDCOCDIN_POS (2) 
#define SYS_ANA_REG14_MICDCOCDIN_MASK (0xFF) 

#define SYS_ANA_REG14_MICDCOCVC_POS (10) 
#define SYS_ANA_REG14_MICDCOCVC_MASK (0x3) 

#define SYS_ANA_REG14_MICDCOCEN_N_POS (12) 
#define SYS_ANA_REG14_MICDCOCEN_N_MASK (0x1) 

#define SYS_ANA_REG14_MICDCOCEN_P_POS (13) 
#define SYS_ANA_REG14_MICDCOCEN_P_MASK (0x1) 

#define SYS_ANA_REG14_MICSINGLEEN_POS (14) 
#define SYS_ANA_REG14_MICSINGLEEN_MASK (0x1) 

#define SYS_ANA_REG14_MICGAIN_POS (15) 
#define SYS_ANA_REG14_MICGAIN_MASK (0xF) 

#define SYS_ANA_REG14_MICDACEN_POS (19) 
#define SYS_ANA_REG14_MICDACEN_MASK (0x1) 

#define SYS_ANA_REG14_MICDACIH_POS (20) 
#define SYS_ANA_REG14_MICDACIH_MASK (0xFF) 

#define SYS_ANA_REG14_MICDACIT_POS (28) 
#define SYS_ANA_REG14_MICDACIT_MASK (0x3) 

#define SYS_ANA_REG14_HCEN_POS (30) 
#define SYS_ANA_REG14_HCEN_MASK (0x1) 

#define SYS_ANA_REG14_MICEN_POS (31) 
#define SYS_ANA_REG14_MICEN_MASK (0x1) 

/* REG_0x4F */
#define SYS_ANA_REG15_ADDR  (SYS_LL_REG_BASE  + 0x4F*4) //REG ADDR :0x4401013c
#define SYS_ANA_REG15_ISEL_POS (0) 
#define SYS_ANA_REG15_ISEL_MASK (0x3) 

#define SYS_ANA_REG15_MICDCOCDIN_POS (2) 
#define SYS_ANA_REG15_MICDCOCDIN_MASK (0xFF) 

#define SYS_ANA_REG15_MICDCOCVC_POS (10) 
#define SYS_ANA_REG15_MICDCOCVC_MASK (0x3) 

#define SYS_ANA_REG15_MICDCOCEN_N_POS (12) 
#define SYS_ANA_REG15_MICDCOCEN_N_MASK (0x1) 

#define SYS_ANA_REG15_MICDCOCEN_P_POS (13) 
#define SYS_ANA_REG15_MICDCOCEN_P_MASK (0x1) 

#define SYS_ANA_REG15_MICSINGLEEN_POS (14) 
#define SYS_ANA_REG15_MICSINGLEEN_MASK (0x1) 

#define SYS_ANA_REG15_MICGAIN_POS (15) 
#define SYS_ANA_REG15_MICGAIN_MASK (0xF) 

#define SYS_ANA_REG15_MICDACEN_POS (19) 
#define SYS_ANA_REG15_MICDACEN_MASK (0x1) 

#define SYS_ANA_REG15_MICDACIH_POS (20) 
#define SYS_ANA_REG15_MICDACIH_MASK (0xFF) 

#define SYS_ANA_REG15_MICDACIT_POS (28) 
#define SYS_ANA_REG15_MICDACIT_MASK (0x3) 

#define SYS_ANA_REG15_HCEN_POS (30) 
#define SYS_ANA_REG15_HCEN_MASK (0x1) 

#define SYS_ANA_REG15_MICEN_POS (31) 
#define SYS_ANA_REG15_MICEN_MASK (0x1) 

/* REG_0x50 */
#define SYS_ANA_REG16_ADDR  (SYS_LL_REG_BASE  + 0x50*4) //REG ADDR :0x44010140
#define SYS_ANA_REG16_HPDAC_POS (0) 
#define SYS_ANA_REG16_HPDAC_MASK (0x1) 

#define SYS_ANA_REG16_VCMSDAC_POS (1) 
#define SYS_ANA_REG16_VCMSDAC_MASK (0x1) 

#define SYS_ANA_REG16_OSCDAC_POS (2) 
#define SYS_ANA_REG16_OSCDAC_MASK (0x3) 

#define SYS_ANA_REG16_OCENDAC_POS (4) 
#define SYS_ANA_REG16_OCENDAC_MASK (0x1) 

#define SYS_ANA_REG16_ISEL_IDAC_POS (5) 
#define SYS_ANA_REG16_ISEL_IDAC_MASK (0x1) 

#define SYS_ANA_REG16_ADJDACREF_POS (6) 
#define SYS_ANA_REG16_ADJDACREF_MASK (0x1F) 

#define SYS_ANA_REG16_NC2_POS (11) 
#define SYS_ANA_REG16_NC2_MASK (0x1) 

#define SYS_ANA_REG16_DCOCHG_POS (12) 
#define SYS_ANA_REG16_DCOCHG_MASK (0x1) 

#define SYS_ANA_REG16_DIFFEN_POS (13) 
#define SYS_ANA_REG16_DIFFEN_MASK (0x1) 

#define SYS_ANA_REG16_ENDACCAL_POS (14) 
#define SYS_ANA_REG16_ENDACCAL_MASK (0x1) 

#define SYS_ANA_REG16_RENDCOC_POS (15) 
#define SYS_ANA_REG16_RENDCOC_MASK (0x1) 

#define SYS_ANA_REG16_LENDCOC_POS (16) 
#define SYS_ANA_REG16_LENDCOC_MASK (0x1) 

#define SYS_ANA_REG16_RENVCMD_POS (17) 
#define SYS_ANA_REG16_RENVCMD_MASK (0x1) 

#define SYS_ANA_REG16_LENVCMD_POS (18) 
#define SYS_ANA_REG16_LENVCMD_MASK (0x1) 

#define SYS_ANA_REG16_DACDRVEN_POS (19) 
#define SYS_ANA_REG16_DACDRVEN_MASK (0x1) 

#define SYS_ANA_REG16_DACREN_POS (20) 
#define SYS_ANA_REG16_DACREN_MASK (0x1) 

#define SYS_ANA_REG16_DACLEN_POS (21) 
#define SYS_ANA_REG16_DACLEN_MASK (0x1) 

#define SYS_ANA_REG16_DACG_POS (22) 
#define SYS_ANA_REG16_DACG_MASK (0x7) 

#define SYS_ANA_REG16_CK4XSEL_POS (25) 
#define SYS_ANA_REG16_CK4XSEL_MASK (0x1) 

#define SYS_ANA_REG16_DACMUTE_POS (26) 
#define SYS_ANA_REG16_DACMUTE_MASK (0x1) 

#define SYS_ANA_REG16_DWAMODE_POS (27) 
#define SYS_ANA_REG16_DWAMODE_MASK (0x1) 

#define SYS_ANA_REG16_CKPOSEL_POS (28) 
#define SYS_ANA_REG16_CKPOSEL_MASK (0x1) 

#define SYS_ANA_REG16_NC1_POS (29) 
#define SYS_ANA_REG16_NC1_MASK (0x3) 

#define SYS_ANA_REG16_BYLDO_POS (31) 
#define SYS_ANA_REG16_BYLDO_MASK (0x1) 

/* REG_0x51 */
#define SYS_ANA_REG17_ADDR  (SYS_LL_REG_BASE  + 0x51*4) //REG ADDR :0x44010144
#define SYS_ANA_REG17_LMDCIN_POS (0) 
#define SYS_ANA_REG17_LMDCIN_MASK (0xFF) 

#define SYS_ANA_REG17_RMDCIN_POS (8) 
#define SYS_ANA_REG17_RMDCIN_MASK (0xFF) 

#define SYS_ANA_REG17_SPIRST_OVC_POS (16) 
#define SYS_ANA_REG17_SPIRST_OVC_MASK (0x1) 

#define SYS_ANA_REG17_NC_POS (17) 
#define SYS_ANA_REG17_NC_MASK (0x7) 

#define SYS_ANA_REG17_HC2S0V9_POS (20) 
#define SYS_ANA_REG17_HC2S0V9_MASK (0x1) 

#define SYS_ANA_REG17_LVCMSEL_POS (21) 
#define SYS_ANA_REG17_LVCMSEL_MASK (0x1) 

#define SYS_ANA_REG17_LOOP2SEL_POS (22) 
#define SYS_ANA_REG17_LOOP2SEL_MASK (0x1) 

#define SYS_ANA_REG17_ENBIAS_POS (23) 
#define SYS_ANA_REG17_ENBIAS_MASK (0x1) 

#define SYS_ANA_REG17_CALCK_SEL0V9_POS (24) 
#define SYS_ANA_REG17_CALCK_SEL0V9_MASK (0x1) 

#define SYS_ANA_REG17_BPDWA0V9_POS (25) 
#define SYS_ANA_REG17_BPDWA0V9_MASK (0x1) 

#define SYS_ANA_REG17_LOOPRST0V9_POS (26) 
#define SYS_ANA_REG17_LOOPRST0V9_MASK (0x1) 

#define SYS_ANA_REG17_OCT0V9_POS (27) 
#define SYS_ANA_REG17_OCT0V9_MASK (0x3) 

#define SYS_ANA_REG17_SOUT0V9_POS (29) 
#define SYS_ANA_REG17_SOUT0V9_MASK (0x1) 

#define SYS_ANA_REG17_HC0V9_POS (30) 
#define SYS_ANA_REG17_HC0V9_MASK (0x3) 

/* REG_0x52 */
#define SYS_ANA_REG18_ADDR  (SYS_LL_REG_BASE  + 0x52*4) //REG ADDR :0x44010148
#define SYS_ANA_REG18_ICTRL_DSPPLL_POS (0) 
#define SYS_ANA_REG18_ICTRL_DSPPLL_MASK (0xF) 

#define SYS_ANA_REG18_FBDIVN_POS (4) 
#define SYS_ANA_REG18_FBDIVN_MASK (0x3FF) 

#define SYS_ANA_REG18_N_MCUDSP_POS (14) 
#define SYS_ANA_REG18_N_MCUDSP_MASK (0x1F) 

#define SYS_ANA_REG18_MODE_POS (19) 
#define SYS_ANA_REG18_MODE_MASK (0x1) 

#define SYS_ANA_REG18_IAMSEL_POS (20) 
#define SYS_ANA_REG18_IAMSEL_MASK (0x1) 

#define SYS_ANA_REG18_HVREF_POS (21) 
#define SYS_ANA_REG18_HVREF_MASK (0x3) 

#define SYS_ANA_REG18_LVREF_POS (23) 
#define SYS_ANA_REG18_LVREF_MASK (0x3) 

#define SYS_ANA_REG18_NC_POS (25) 
#define SYS_ANA_REG18_NC_MASK (0x7F) 

/* REG_0x53 */
#define SYS_ANA_REG19_ADDR  (SYS_LL_REG_BASE  + 0x53*4) //REG ADDR :0x4401014c
#define SYS_ANA_REG19_AMSEL_POS (0) 
#define SYS_ANA_REG19_AMSEL_MASK (0x1) 

#define SYS_ANA_REG19_MSW_POS (1) 
#define SYS_ANA_REG19_MSW_MASK (0x1FF) 

#define SYS_ANA_REG19_TSTCKEN_DPLL_POS (10) 
#define SYS_ANA_REG19_TSTCKEN_DPLL_MASK (0x1) 

#define SYS_ANA_REG19_OSCCAL_TRIG_POS (11) 
#define SYS_ANA_REG19_OSCCAL_TRIG_MASK (0x1) 

#define SYS_ANA_REG19_CNTI_POS (12) 
#define SYS_ANA_REG19_CNTI_MASK (0x1FF) 

#define SYS_ANA_REG19_NC_POS (21) 
#define SYS_ANA_REG19_NC_MASK (0x1) 

#define SYS_ANA_REG19_SPI_RST_POS (22) 
#define SYS_ANA_REG19_SPI_RST_MASK (0x1) 

#define SYS_ANA_REG19_CLOSELOOP_EN_POS (23) 
#define SYS_ANA_REG19_CLOSELOOP_EN_MASK (0x1) 

#define SYS_ANA_REG19_CALTIME_POS (24) 
#define SYS_ANA_REG19_CALTIME_MASK (0x1) 

#define SYS_ANA_REG19_LPFRZ_POS (25) 
#define SYS_ANA_REG19_LPFRZ_MASK (0x3) 

#define SYS_ANA_REG19_ICP_POS (27) 
#define SYS_ANA_REG19_ICP_MASK (0xF) 

#define SYS_ANA_REG19_CP2CTRL_POS (31) 
#define SYS_ANA_REG19_CP2CTRL_MASK (0x1) 

#ifdef __cplusplus 
}                  
#endif             
